AM335x GPMC in AAD-mode

I used the Starterkit driver functions:

    GPMCAddrDataMuxProtocolSelect( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_1, GPMC_MUXADDDATA_AADMUX);
    GPMCAddrDataMuxProtocolSelect( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, GPMC_MUXADDDATA_AADMUX);

    GPMCDevTypeSelect( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_1, GPMC_DEVICETYPE_NORLIKE );
    GPMCDevTypeSelect( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, GPMC_DEVICETYPE_NORLIKE );

    GPMCFclkDividerSelect(SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_1, GPMC_FCLK_DIV_BY_4);

    GPMCDevSizeSelect( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_1, GPMC_DEVICESIZE_16BITS);
    GPMCDevSizeSelect( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_2, GPMC_DEVICESIZE_16BITS);

and the resulting register set is following (timing not optimized yet) :
Config1: 0x00001103
Config2: 0x000f0f00
Config3: 0x22040413
Config4: 0x0a056a15
Config5: 0x000a100a
Config6: 0x0a0701c1

IMHO this is set to 16-bit-mode.

---
BTW: The driver reset funktion does not reset the config register
and the driver sets bits only (without clear old existing flags before).
I added manually writing zeros into the config registers before init.
Is this 'ok' or maybe a track to the reason of the probem?

no surprise:

#define START_ADDR_SRAM            (0x01000000u)
GPMCBaseAddrSet( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_1, START_ADDR_SRAM>>24 );
GPMCMaskAddrSet( SOC_GPMC_0_REGS, GPMC_CHIP_SELECT_1, GPMC_CS_SIZE_16MB);

Config7: 0x00000f41
(16 MB size, CSVALID, Startaddress 16MB)

The 1st 256 bytes of SRAM-test are working proper. So MMU and Startaddress

big surprise:
- I use AM3352 on a module (phyCORE) with NAND, but now booting from sd-card
- CS0 (NAND) is enabled (how does this?) (Config7_0=0x0f40 - should not disturb)
But a disabled CS0 changes nothing. Sorry.

Any other idea? What's about the conflicted descriptions of AAD-mode?
Should the 8/16-Bit flag switch the muxed address byte/word size?
(IMHO AAD-mode does not make sense handling 2 single address bytes on a 16 bit bus; ref. Fig 7-15, 7-16)

Thanks and best regards

Bastian

JFYI: reset values of GPMC-config registers CS1 are:
Config1: 0x00401000
Config2: 0x00101001
Config3: 0x22060514
Config4: 0x10057016
Config5: 0x010f1111
Config6: 0x8f070000
Config7: 0x00000f00
i.e. init is done while CSVALID is disabled

The behaviour seems to be like Fig. 7-15/Fig. 7-16:
senior addresses at 1st strobe are A[16:9], at 2nd strobe A[8:1].
To latch A[16:1] I can easier use AD-mode.

BUT I want to get A[27:17] and A[16:1] like described in 7.1.2.3 (spruh73i.pdf)

I call
    "GPMCModuleSoftReset(SOC_GPMC_0_REGS);
     while (GPMCModuleResetStatusGet(SOC_GPMC_0_REGS) == 0);"
After then Config1 contains 0x00401000; the manual specifies a reset value of 0000;
At least the CSVALID-bit in config7 is 0.

Code Composer Studio 5.4.0, Starterware 02.0.0.7

I assumed the starterware drivers are well known and proven. We can discuss on bit-layer too.
Let's go back to topic:

The manual does 2 conflicting specifications.
a) one of them is a documentation fault (the not-working from 7.1.2.3, and I can throw away my prototype)
    or
b) there must be an undocumented configuration flag
    or
c) the information is hidden well in these 4737 pages; please help

Am I the 1st using GPMC in AAD-mode?

It is not a matter of external circuit. I used a osci to watch nCS1, nADS, AD0,  AD8 ...
and AD8..16 were always zero.

I tested the "normal" A/D-muxed mode, which is described well. AD8..16 were zero too.
So I found, that the LCD-Init overwrote the GPMC pin muxing.

=> now it looks better

(pardon me - of course AD8..15)

I think the legends of Figure 7-15 and 7-16 in spruh73 should be so:

remaining question: are A[27:17] inside A/D[15:0] right- or left-aligned.
Anyway I assumed left-aligned - this was wrong. rrrgh