AM335x McSPI

Although this is not the StarterWare Forum I will show a possible solution that works for me (after days of testing). Maybe some other reader will find it helpful.

Transmit:
One trick is to have the chip select forced before activating the channel. Otherwise it does not work. Second trick, as Biser already mentioned, is to fill-up the transmit FIFO after activating the channel.
Activating TURBO mode reduces the gaps between bytes from around 200ns to less than 100ns. Maybe this is also dependend of the used SPICLK.

Receive:
The third trick is to test RXFFE bit and RXS bit to be shure that all the bytes got read. It looks as if the last byte from the FIFO falls into the receive register (SPI_RX) after reading the second last byte and then the RXFFE bits gets set. So one has to test RXS bit to see if there is one more byte to read.
Reading the receive FIFO is possible after deactivate the chip select and after deactivate the channel.

So the code now looks like this:

{
  volatile Uint32 dummy;

  // Chip Select aktivieren
  HWREG(SOC_SPI_0_REGS+MCSPI_CHCONF(0))=(HWREG(SOC_SPI_0_REGS+MCSPI_CHCONF(0)) | MCSPI_CH0CONF_FORCE);

  // Kanal 0 freigeben
  HWREG(SOC_SPI_0_REGS+MCSPI_CHCTRL(0))=(HWREG(SOC_SPI_0_REGS+MCSPI_CHCTRL(0)) | MCSPI_CH0CTRL_EN_ACTIVE);

  // Zu sendende Bytes in der FIFO ablegen
  HWREG(SOC_SPI_0_REGS+MCSPI_TX(0))=0x91;
  HWREG(SOC_SPI_0_REGS+MCSPI_TX(0))=0x92;
  HWREG(SOC_SPI_0_REGS+MCSPI_TX(0))=0x93;
  HWREG(SOC_SPI_0_REGS+MCSPI_TX(0))=0x94;

  // Warten, bis Transmit FIFO leer ist
  while((HWREG(SOC_SPI_0_REGS+MCSPI_CHSTAT(0)) & MCSPI_CH0STAT_TXFFE)==0)
  {
    // Falls ein Byte in der Empfangs Queue vorhanden ist, dieses auslesen
    if ((HWREG(SOC_SPI_0_REGS+MCSPI_CHSTAT(0)) & MCSPI_CH0STAT_RXFFE)==0)
    {
      dummy=HWREG(SOC_SPI_0_REGS+MCSPI_RX(0));
    }
  }
  // Kanal 0 sperren
  HWREG(SOC_SPI_0_REGS+MCSPI_CHCTRL(0))=(HWREG(SOC_SPI_0_REGS+MCSPI_CHCTRL(0)) & ~MCSPI_CH0CTRL_EN_ACTIVE);

  // Chip Select deaktivieren
  HWREG(SOC_SPI_0_REGS+MCSPI_CHCONF(0))= (HWREG(SOC_SPI_0_REGS+MCSPI_CHCONF(0)) & ~MCSPI_CH0CONF_FORCE);

  // Solange noch Daten in der Empfangs Queue vorhanden sind, diese auslesen
  while(((HWREG(SOC_SPI_0_REGS+MCSPI_CHSTAT(0)) & MCSPI_CH0STAT_RXFFE)==0) ||
        ((HWREG(SOC_SPI_0_REGS+MCSPI_CHSTAT(0)) & MCSPI_CH0STAT_RXS)!=0))
  {
    dummy=HWREG(SOC_SPI_0_REGS+MCSPI_RX(0));
  }
}

I really expect TI to come up with this. Maybe is is necessary that TI rewrites the McSPI description in the TRM so that all the mechanism get a bit clearer.