how to flash nand flash via Gel file and nand-flash-writer.out

Vivek,

The prompt will be visible in the debugger once you start running the program.

Thanks. Got it. I found gel file was not executing. After filling right parameters for DDR2 it started running. Now stuck in nand flash. It fails and says init failed. I found array does not have data of our nand flash chip. We are using MT29F16G08ABACAWP. Do you have updated nand writer. We are using 5.04 tool chain and AM3892.

Vivek,

Try to add the data that you receive to the array and see whether it continues from there.

Hi Renjith,

thanks again. yeah i changed the code done the hard coding into nand.c: NETRA_flashGetDetails()

 hNandInfo->manfID = devID[0]; // Use JEDEC manufacturer ID from Parameter Page
 hNandInfo->devID = (Uint8) devID[1]; // Use Device ID from the standard READID command
 hNandInfo->dataBytesPerPage = 1024 << (devID[3] & 0x3); // Last two bits give Page size
 hNandInfo->spareBytesPerPage = 224; // 32 << ((devID[3] & 0xF) >> 2); // Bit 2,3 bit give spare area
 blocksize = 0x80000; // 64 << ((devID[3] >> 4) & 0x3); // Bit 4,5 give Block size;
 hNandInfo->pagesPerBlock = 128; // (blocksize * 1024) / hNandInfo->dataBytesPerPage;
 hNandInfo->numBlocks = 4096;

this way it at least started executing. In the end it gives

NAND flashing successful!

But after this u-boot is not working.

kindly check my understanding:

1. Nand flash writer will copy u-boot.noxip.bin to Nand Flash chip.

2. Upon hard boot, ARM ROM Code will execute. it will copy the u-boot.noxip.bin from Nand Flash chip to OCMC0 RAM ( 0x4040 0000). 

3. ARM ROM Code will then copy the different section like TEXT etc (depending on Linker script) to DDR2 RAM at

0x8000 0000.

4. ARM ROM Code will pass the control to start.S.

5. start.S will pass control to start_armboot() c funtion in board.c

Kindly check if this is correct.

Next my questions.

1. After Hard boot: after waiting for 3 min, i put the JTAG, then checked 0x4040 0000 location it does have some thing copied but that did not match with u-boot.noxip.bin binary. i dont known if this should match or not.

2. U-boot code has u-boot-2010.06-psp04.04.00.01\include\config.h has

#define CONFIG_SYS_NO_FLASH,

Is this required or not. Please suggest

3. Uboot code:

 u-boot-2010.06-psp04.04.00.01\include\configs\ti8168_evm.h

# define NAND_BASE (0x08000000)

Is this the address from where u-boot.noxip.bin is taken from Nand Flash chip.

4. how to trouble shoot uboot. some pointers. Serial (Console is Not working). we can not use JTAG, since uboot does not run directly from RAM.

really appreciate your effort in reply to my queries.

Regards

Vivek

we are using customized board based on AM3892. Flash Memory is MT29F16G08ABACAWP. Console is connected to UART0. i have modified the code for UART0 which was earlier for UART2.

regards

Vivek

when after hard reset, I put debugger , and checked

CONTROL_STATUS : 0x312

BOOTSTAT : 0x00

CONTROL_STATUS should have 0x12 because it nand boot, but why 3 is coming I don't know. Also bootstat should save last error, but it is not saving it. it should not be 0x00.

Regards

Vivek

Hi Vivek,

Sorry for my delayed response.

1. What is the size of the image that you are flashing? 

2. Have you confirmed your DDR settings and verified whether DDR works fine?

3. To make sure that your u-boot is correct, load the u-boot.bin image to the load address (OCMC memory) specified in the map file and then jump to the start address. Then you might see the logs properly, if its running fine.

4. In your custom board, is the UART0 used for serial console?

5. Check the ARM's PC register to see where the code is getting executed currently, using CCS.

Hi Renijth,

here are your answeres:

1. What is the size of the image that you are flashing? 

[vivek] i flashing uboot.noxip.bin which 208KBytes less then 255KB.

2. Have you confirmed your DDR settings and verified whether DDR works fine?

[Vivek] Yes, after loading gel file i did Write and then read of memory in 0x80000000 via JTAG. we tested random locations upto last limit.

i have changed the LISA MAP, since there is only one chip select connected to DDR2 Emif 0.

 WR_MEM_32(DMM_LISA_MAP__0, 0x80400100);
 WR_MEM_32(DMM_LISA_MAP__1, 0x00000000);
 WR_MEM_32(DMM_LISA_MAP__2, 0x00000000);
 WR_MEM_32(DMM_LISA_MAP__3, 0x00000000);
WR_MEM_32(DMM_PAT_BASE_ADDR, 0x80000000);

3. To make sure that your u-boot is correct, load the u-boot.bin image to the load address (OCMC memory) specified in the map file and then jump to the start address. Then you might see the logs properly, if its running fine.

[Vivek]: i did same yesterday. but found u-boot is crashing and jumping on 90000000h address from board_init() function. i am not able to see from where it is jumping. Now there is no 0xC0000000 address space.

Does changing LISA impacting peripheral init?

4. In your custom board, is the UART0 used for serial console?

[Vivek} Yes

5. Check the ARM's PC register to see where the code is getting executed currently, using CCS.

same as 3.

Please suggest:

1. what is NAND_BASE (0x08000000)

2. there is one function which is called from assembly s_init(u32 in_ddr) present in evm.c

Parameter in_ddr is coming as 1, and for initializing DDR2 memory we need this as 0.

If you know Please suggest  what is in_ddr as 1.

Regards

Vivek

Looks like your LISA mapping is not proper. But I'm currently not sure what is the right value as I'm not clear about your memory configurations. 

vivek gupt said:

what is NAND_BASE (0x08000000)

NAND is not really memory mapped. Also the address mapping depends on the GPMC_CONFIG7 register values, depending on your chipselect.

vivek gupt said:

If you know Please suggest  what is in_ddr as 1.

in_ddr means whether the current code is already running in DDR or from OCMC RAM?