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L4 Interconnect access time

Patrick Ruf
Genius 4965 points

Hi,

Can anyone from TI tell us the fastest possible access time for internal peripheral registers (at L4 interconnect)?

For example access tim to MCSPI_CHSTAT0?

I measured a time of approx. 0.1861us with CPU running full speed (720MHz) and MMU enabled. Register memory space not cached.

I want to make shure that nothing else is wrong. So I need a value that I can validate.

Thanks.
Best regards,
Patrick