Dear Sir,
I am working on L1D/L1P/L2 RAM and Cache memory using DM6437 and CCS v5.3.0.
I am not using DSP BIOS.
As per earlier discussion in the forum I tried few instructions.
Off late I used "cslr_cache.h" to directly configure L1D cache.
#define CSL_CACHE_L1DCFG_MODE_32K (0x00000005u)
#define CSL_CACHE_MAR_PC_CACHEABLE (0x00000001u)
Cache_regs->MAR[0] &= CSL_CACHE_MAR_PC_CACHEABLE;
Cache_regs ->L1DCFG &= CSL_CACHE_L1DCFG_MODE_MAX;
When I debug and run the code, the value of L1D CACHE Register in the Register Window is not changing.
What might be the error ?
Am I configuring it correctly ?
Since these registers are memory mapped I tried configuring L1D cache using it address, but still the value of Cache Register after debug - run is not changing.
I changed the .cmd file accordingly.
.stack > L1DSHRAM2
.data > L1DSHRAM2
I am getting doubts like,
Is my cache really configured, if yes then how can I know in which address my data is getting saved?
I am stuck and unable to find relevant document.
Can you suggest me with any solution ?
Thanking you,
Regards,
S Sandeep