I am looking for a way to control when the data are placed on the bus with respect to the transmit clock.
The documentation states that depending on the setting of CLKINVx of the UPICR that data signals "will align" with either the rising or falling edge of the clock. Does this mean they are valid on the rising/falling edge of the clock or changing on the rising/falling edge of the clock?
I have tried both settings of the CLKINVx bit in transmit mode and the time when the data is changing on the bus is not changing with respect to the clock. I am using an external clock, the 2x clock. Does this setting only apply when using the internal clock?
Hunter
