• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 533 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Aboult the throughput of keystone's MSMC

Yi Yin1
Intellectual 430 points

Hi 

I am looking for information about memory performance in the C6678 DSP.

I understood that:

MSMC SRAM has 4 memory banks of 256 bits, and  all 4 banks can be accessed simultaneously by separate cores or other system masters.

But in the Application Report  Throughput Performance Guide for C66x KeyStone Devices(SPRABK5A1) 

5.3 Scenario 3: EDMA Transfer From MSMC SRAM to MSMC SRAM,

I found the following description:

"so there is only one transfer happening at a time. "

"it cannot do both reads and writes at the same time." 

Is that contradiction？

Which is correct？

Or I misunderstood it?

Thank you.

Yin




  • 0
    TI__Guru* 81335 points

    Hi Yi,

    Your understanding is correct. 

    In the given scenario, both read and write operations are happening at the MSMC SRAM.

    All the banks can be accessed simultaneously but the read & write operation can not be at the same time. 

    The transfer throughput is depends on read and write operation.

    Thanks.

  • 0 in reply to Raja
    Intellectual 430 points

    Hi Rajasekaran

    Thank you for a reply!

    >All the banks can be accessed simultaneously but the read & write operation can not be at the same time. 

    I understand that the 4 banks MSMC SRAM can be read  simultaneously  or  written simultaneously.

    Is that correct?

    But if MSMC SRAM has 256bits per bank， why the read & write operation can not be at the same time?

    Is there a more detailed description?

    Thanks!

    Yin




  • 0 in reply to Yi Yin1
    TI__Mastermind 30825 points

    Yin,

    There are multiple 256 bit ports into the MSMC memory.  There is one slave port for each CorePac the device has, there's two System Slave ports for other device accesses, One EMIF Master, and only one System Master port.

    The transactions for an EDMA MSMC Read and Write go through the same port, which can only do reads or writes in the same cycle.

    While other peripherals/CorePac's can simultaneously be accessing the MSMC memory banks via other ports that isn't being accessed during this MSMC-MSMC read/write on the same cycle.

    Best Regards,

    Chad