am335x LCD Timing + HDMI TDA19988 sdk6

Hi Ram,

Is this behaviour observed both when the monitor is plugged in and when it is plugged out?

You may also try to look for an advice about the implementation of HDMI in the BeagleBone forums, since the BeagleBone Black already has this feature.

Best regards,
Miroslav

Hi Miroslav,

This is observed all the time, doesnt matter whether the monitor is plugged or not.

It is a little complicated with HDMI. Beagleboard support for this chip is only in the non-TI kernel. I guess that too with X windows. Since the driver for TDA1988 is under DRM drivers, I have no way of enabling it in TI SDK kernel. So I wrote a standard I2C driver that initializes the chip and writes constant timing values (in this case for 800x600 display). But I am unable to test whether this method of initing the chip works, if I am unable to get the lcd controller to give out proper signals. Right now I just get mode out of range in my monitor.

I changed the IFB_DA8XX_CONSISTENT_DMA_SIZE = 14 in kernel config and added the above mentioned lcd timing parameters to the da-fbxxx file.

Kernel boot messages suggest lcd controller is properly inited, but somehow still defaults to this 64MHz pclock with a wierd virtual vertical resolution. I have no idea where this mode comes from. It is specified nowhere in the driver file.

The timings mentioned in my first post, seems to be correct after cross checking in some other forums. Do I need to change some other file / settings to change the display resolution ?

Thanks a lot in advance.

Ram

Your timings reported by the fbset utility seem correct, except for the pixel clock period (15625ps).

I'd suggest you check what happens inside the da8xxfb_pixel_clk_period() function inside the da8xx-fb driver using some prints.

Best regards,
Miroslav

Hi Miroslav,

After snooping around with printks as you suggested, I have zeroed in on the problem area.

The lcdc clock is 192000000. the divisor for the pixeclock is calculated by dividing the pixelclock we give in panel configuration with the lcdc clock. so for example : required pixclock 75MHz. Divisor is 192MHz / 75MHz => 2.56 in unsigned int divisiion it is 2! so the resulting clock is ~ 96MHz. in smaller clock resolutions, the result is okay, but in higher resolutions, it is impossible to get the pixclock we want.

Is it possible to increase the main lcdc clock frequency ? I see that the main clock is assigned in the probe function

fb_clk = clk_get(&device->dev, NULL);

I cannot believe that this is true, because it is impossible to get higher resolutions with this method. I have to search for a resolution that has 95MHz pixclock or 64MHz. 95MHz is the highest supported pixclock, since the div field cannot be 0 or 1 according to datasheet.

Have I understood this wrong ?

Can anyone post me timings that work for higher resolutions like 1024x768 or 1366x768 ?

Thanks a lot in advance.

Ram

Hi Biser,

Thank you very much for pointing this out. This makes sense. I could theoritcally adjust display pll for the output clock that I want.

I see that in board config file there is a function that sets display pll to 300000000 rate. Dont know what unit this is. I tried chaging this to various values and it has no effect on the lcdc clock. it stays always at 192000000. It does not return error, but the end result in da8xx-fb.c is always 192000000. Do you know where I will be able to change this value ? I am using linux sdk6.00.

Thanks again and best regards.

Ram

Hi Biser,

I have 24MHz at XTALIN.

By the way, this 300MHz setting in board config for display pll is strange, as according to datasheet only 200MHz is the maximum allowed range. And anyways da8xx-fb.c seems to ignore this. I cant find out where else display pll is being set.

Thanks again for your effort.

Ram

Hi Biser,

This is good news. At least I know where the problem lies. I tried searching where this clock is selected. The best I can find now is in clock33xx_data.c

static const struct clksel lcd_clk_mux_sel[] = {
	{ .parent = &disp_pll_clk, .rates = div_1_0_rates },
	{ .parent = &sysclk2_ck, .rates = div_1_1_rates },
	{ .parent = &per_192mhz_clk, .rates = div_1_2_rates },
	{ .parent = NULL },
};

static struct clk lcd_gclk = {
	.name		= "lcd_gclk",
	.parent		= &disp_pll_clk,
	.init		= &omap2_init_clksel_parent,
	.clksel		= lcd_clk_mux_sel,
	.clksel_reg	= AM33XX_CLKSEL_LCDC_PIXEL_CLK,
	.clksel_mask	= AM33XX_CLKSEL_0_1_MASK,
	.ops		= &clkops_null,
	.recalc		= &followparent_recalc,
};

But I cant find where the lcd_clk_mux_sel is being used to select the per_192mhz_clk.

Can you or miroslav help me find where to change this setting ?

Thanks again for the awesome help.

Ram

Hi Ram,

Please find the _get_clksel_by_parent() function inside <linux_dir>/arch/arm/mach-omap2/clkt_clksel.c. It returns the correct clksel structure for a given clk & parent. It is a private function and all the caller functions are inside the same file.

Best regards,
Miroslav

Hi Ram,

I also meet the same question,I have a custom AM335x board and HDMI is TDA19988.

My kernel vision is linux-3.2.0,Now I want to use the HDMI ,but I don't know whether  the code can be supported by my kernel ,so I need your help.

Hi Song,

    Although a long time has passed, I got the same problem as yours. Do you solve the problem now?  If so would you please give me some help.

Hope to hear from you soon. Thanks in advanced!