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am335x boot nand timings

jags vg
Intellectual 865 points

Hi All,

I am looking at the board-am335xevm.c inside am335x jb 4.2.2 / kernel -3.2.0.

There i have found ,

static struct gpmc_timings am335x_nand_timings = {
.sync_clk = 0,

.cs_on = 0,
.cs_rd_off = 44,
.cs_wr_off = 44,

.adv_on = 6,
.adv_rd_off = 34,
.adv_wr_off = 44,
.we_off = 40,
.oe_off = 54,

.access = 64,
.rd_cycle = 82,
.wr_cycle = 82,

.wr_access = 40,
.wr_data_mux_bus = 0,
};

can anyone explain me how this timings are calculated?

I have read related sections in TRM but still iam not able to understand the same.

I have some doubt.

in above structure :

.cs_rd_off = 44,
.cs_wr_off = 44,

From TRM , the above value are 5 bit long. so maximum can be 0x1F (31).

then how it is 44?

How above values are going to be written in gpmc configuration registers?



-------------------------------------------------------------------------------------------------------------------------

Thanks,

Jags Gediya

  • 0
    TI__Guru**** 393215 points
    These times are in GPMC clock cycles. You have to search the source code about which functions use them and how they are transformed to register values.
  • 0 in reply to Biser Gatchev-XID
    Expert 1100 points

    The calculation in the kernel is here: /arch/arm/mach-omap2/gpmc.c

    function set_gpmc_timing_reg is called to set the register and the time from the config structure is passed in.  This function then calls gpmc_ns_to_ticks to convert to ticks for setting the register value:

    unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
{
	unsigned long tick_ps;

	/* Calculate in picosecs to yield more exact results */
	tick_ps = gpmc_get_fclk_period();

	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
}

    Basically the times listed in the configuration are in Nanoseconds and are converted to GPMC Clock Cycles and set accordingly.  fclk is 100MHz so period is 10000ps.

    So the 44 from your example is 44ns which means:

    (44 * 1000 + 9999)/10000 = 5

    So 5 GPMC clock cycles is what is used for that time.

  • 0 in reply to Jarrod Cook
    Intellectual 360 points

    hi  Ti,

    i found that the nand ready/busy is not implemented in the kernel linux-3.2.0-psp04.06.00.10 for am335x

    is it true ? did i miss something ? 

    if not implemented, how to added it ? did we have any patches ?

    if rdy/busy is implemented i think the delay implementation is not required. is it ?

    for ref:

    --------

    drivers/mtd/nand/omap2.c

    /*
    * If RDY/BSY line is connected to OMAP then use the omap ready
    * funcrtion and the generic nand_wait function which reads the status
    * register after monitoring the RDY/BSY line.Otherwise use a standard
    * chip delay which is slightly more than tR (AC Timing) of the NAND
    * device and read status register until you get a failure or success
    */
    if (pdata->dev_ready) {
    info->nand.dev_ready = omap_dev_ready;
    info->nand.chip_delay = 0;
    } else {  /* controle comes here */
    info->nand.waitfunc = omap_wait;
    info->nand.chip_delay = 50;
    }

    can u please calrify this ?

    regards,

    Nagendra