Thank you for all your support.
During debugging unstable DDR3 memory access, I found out "unexpected write access timing" as attached. It seems that DQ and DQS timing is shifted by 45 degree, and I believe this should be right in the center. I was wondering if any of you could advise me how to fix this. The configuration is below. I appreciate this.
DSP: TMS320C6657CZH25
memory, Micron: MT41J128M16HA-125
8 banks open for interleaving
RZQ/2
RZQ/2
RZQ/7
CWL = 8
32-bit bus width
CAS = 11
14 row bits
8 bank SDRAM
Use DCE0# for all SDRAM accesses
1024-word page