The manul says that in contrast to the DMA4_CSRi registers, the DMA4_IRQSTATUS_Lj registers are updated regardless of the corresponding bits in the DMA4_IRQENABLE_Lj registers.
It means that no matter the corresponding logic channel interrupt control bits in DMA4_IRQENABLE_Lj are enabled or not, the corresponding bit in DMA4_IRQSTATUS_Lj (j from 0 to 3) all will be set if the logic channel generates a interrupt signal, but the DMA4_CSRi register are updated only when the corresponding bit in DMA4_CICRi was enabled.
It goes without saying that if I configure the DMA4_CSRi register to enable interrupt of the logic channel i and disable the corresponding interrupt in DMA4_IRQENABLE_Lj, it will update the DMA4_IRQSTATUS_Lj but not send the interrupt signal to the corresponding interrupt controler when the logic channel i generates a interrupt signal.
I want to know what I understand is right or not.
If it's wrong, please clear it for me.
If it's right, I would miss in the following case:
(1)The DMA4_CICR0 and DMA4_CICR1 are configured to enable interrupt of the logic channel 0 and 1.
(2)The DMA4_IRQENABLE_Lj's first bit is set but the other bits are cleared.
Firstly, the logic channel 1 generates a interrupt signal, it will set the DMA4_IRQSTATUS_Lj's second bit.
Then, the logic channel 0 generates another interrupt signal, it will set the DMA4_IRQSTATUS_Lj's first bit and send the interrupt signal to the corresponding interrupt controler and the software enteres the corresponding interrupt service routine.
To indentify which logic channel generates the interrupt, the software should read the DMA4_IRQSTATUS_Lj register, but there are two high level bits in the DMA4_IRQSTATUS_Lj register. In my options, the software has to read the DMA4_IRQENABLE_Lj to identify the interrupt source. Is there any other better way for this case?
