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AM3352 - problem with GPMC module with NAND Flash

Other Parts Discussed in Thread: AM3352

Hello,

My customer is faceing a problem with AM3352 processor with NAND256W3A0BZA6 attached.
Could you help to configure the GPMC module to work properly with above NAND Flash.
Issue is that CS signal needs to be in Active state since command is send until the data is valid.
Since now customer couldn't configure memory controller to do so.
As workaround CS signal is connected to GPIO, it works but it's not a proper solution.

Could you give me some hints, or examples how to configure memory controller?

thanks in advance

MK

  • Hi Marcin,
     
    The AM335X GPMC is limited only to "chip select don't care" NAND devices. This is pointed out in the AM335X Technical Reference Manual, Rev. I, section 7.1.3.3.12.
  • I think it might still be possible:  if I'm reading 7.1.3.3.9.1 and 7.1.3.3.9.2 right, if CS is programmed to be low during the entire access and no turnaround/cycle2cycle gap has been configured, CS won't be lifted between pipelined back-to-back accesses.  If wait monitoring is enabled for reads, and OEONTIME is programmed to a sufficient value, the busy signal should freeze the read access with nRE still high as desired.

    There must be no gap between the command/address writes (so enable NANDFORCEPOSTEDWRITE) and subsequent reads (enable prefetching engine immediately after posting the address-write). The documentation warns that using wait monitoring will effectively lock up the GPMC until the read access completes, but if DMA is used this isn't a problem I think.

    It's still a long shot though, and even if you're lucky and it does work, it would still be a rather fragile construction. If switching to a more compatible NAND flash is possible, it should definitely be preferred.