fpga gpmc timings

Hello Jags,

The timing values/parameters for OMAP4460 are described in OMAP4460 Data Manual book. Refer to section - 5.4.1.4 GPMC/NAND Flash Interface—Asynchronous Mode.

#Q1: But How can we decide that values? - In the data manual are shown equations for calculating of each timing parameter. Use those equations for your case and use the information in following tables:

- Table 5-12. GPMC/NAND Flash Timing Conditions—Asynchronous Mode
- Table 5-13. GPMC/NAND—Asynchronous Mode—Internal Parameters
- Table 5-15. GPMC/NAND Flash Switching Characteristics—Asynchronous Mode

#Q2: Will available nand and gpmc driver work for above configurations? - You can find the definitions of the gpmc timing parameters in the file - arch/arm/mach-omap2/gpmc-nand.c

For more information see sections in OMAP4460 TRM: - 15.4.4.10 Timing Setting and
15.4.4.13.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode

Best regards,

Yanko

Hi Yanko,

Thanks for your informative reply.

I have gone through the omap4460 data manual, particularly for nand related timings.

There they have defined some parameters like below.

---------------------------------------------------------------------------------------------------------------------------------------

A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) *
GPMC_FCLK period
C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay))
* GPMC_FCLK period
D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK period
E = (WrCycleTime - WEOffTime * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK
period
F = (ADVWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay )
* GPMC_FCLK period
G = (CSWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay ) *
GPMC_FCLK period
H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK period
I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK period
J = ((AccessTime - OEOffTime) * (TimeParaGranularity + 1) - 0.5 * OEExtraDelay)) * GPMC_FCLK
period
K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK period
L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK period
M = (CSRdOffTime - OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ) *
GPMC_FCLK period

-------------------------------------------------------------------------------------------------------------------------------------

Through above calculation we can get A,B,C...etc. etc.

But my doubt is, What values we should provide for below parameters inside gpmc_timings structure ?

WEOffTime

WEOnTime

CSOnTime

ADVOnTime......etc. etc.

Through this value only we are going to calculate A, B, C...etc.

Hello Jags,

There is a dedicated structure in gpmc.h file - (/arch/arm/plat-omap/include/plat/gpmc.h). In this structure are defined all timings parameters for GPMC modules -

/*
 * Note that all values in this struct are in nanoseconds except sync_clk
 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
 */
struct gpmc_timings {
    /* Minimum clock period for synchronous mode (in picoseconds) */
    u32 sync_clk;

    /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
    u16 cs_on;        /* Assertion time */
    u16 cs_rd_off;        /* Read deassertion time */
    u16 cs_wr_off;        /* Write deassertion time */

    /* ADV signal timings corresponding to GPMC_CONFIG3 */
    u16 adv_on;        /* Assertion time */
    u16 adv_rd_off;        /* Read deassertion time */
    u16 adv_wr_off;        /* Write deassertion time */

    /* WE signals timings corresponding to GPMC_CONFIG4 */
    u16 we_on;        /* WE assertion time */
    u16 we_off;        /* WE deassertion time */

    /* OE signals timings corresponding to GPMC_CONFIG4 */
    u16 oe_on;        /* OE assertion time */
    u16 oe_off;        /* OE deassertion time */

    /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
    u16 page_burst_access;    /* Multiple access word delay */
    u16 access;        /* Start-cycle to first data valid delay */
    u16 rd_cycle;        /* Total read cycle time */
    u16 wr_cycle;        /* Total write cycle time */

    /* The following are only on OMAP3430 */
    u16 wr_access;        /* WRACCESSTIME */
    u16 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
};

The values for GPMC timings are set by the dedicated function in the gpmc.c file (/arch/arm/mach-omap2/gpmc.c):

int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
    int div;
    u32 l;

    div = gpmc_cs_calc_divider(cs, t->sync_clk);
    if (div < 0)
        return -1;

    GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
    GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
    GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);

    GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
    GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
    GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);

    GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
    GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
    GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
    GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);

    GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
    GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
    GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);

    GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);

    if (cpu_is_omap34xx()) {
        GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
        GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
    }

    /* caller is expected to have initialized CONFIG1 to cover
     * at least sync vs async
     */
    l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
    if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
#ifdef DEBUG
        printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
                cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif
        l &= ~0x03;
        l |= (div - 1);
        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
    }

    return 0;
}

#Q: What values we should provide for below parameters inside gpmc_timings structure?

- For example: You must set a value for WEONTIME - GPMC_CONFIG4_i[19:16] WEONTIME - nWE assertion time from start cycle time: 0x0: 0 GPMC_FCLK cycle

Values in bit-field                  Clock Cycle

         0x1:                            1 GPMC_FCLK cycle
...
         0xF:                            15 GPMC_FCLK cycles

When you calculate A,B,C values in ns, then you must convert those values in clock cycles. After that set those values in the corresponding bit-fields for timings parameters.

Best regards,

Yanko 

More useful stuff for "how to calculate timings". it it about nand but still helpful to get the general idea.  http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/169220/1080289.aspx#1080289