I am using the C5507 DSP in an application which does not require the USB peripheral. In reading spra078d (Disabling the Internal Oscillator on the VC5503/C5506/C5507/C5509/C5509A DSP), I see that "To disable the internal clock oscillator, both the DSP clock generator and the USB clock generator must be enabled before the IDLE power-down sequence can be initiated". The current board design uses a crystal frequency which does not allow the USB DPLL to generate the required 48 MHz clock. Since I am not actually using the USB peripheral, does the clock need to be configured to exactly 48-MHz or can I just configure it to something close (say 46.08 MHz)? I am hoping this will work since all I need to do is have both (DSP/USB) clock generators enabled so the internal clock oscillator is also disabled when I idle the CLKGEN domain.
Thanks!