I'm using a different codec that provides external i2s framing ( Different than the dm365 evm) . A sample is 64 bits: 32 on left, then 32 on the right channel.
However the transfer is not correct. The correct transfer params are 2x32 bits McBSP capture, then use the EDMA controller to strip off the correct bits. Here's what is supposed to be happening
|------ ONE Capture ----------------------------------------------------------------------|
|-- Left ------------------------------------|-- Right -----------------------------------|
<Byte_A> <Byte_B> <Byte_C> <Byte_W> <Byte_X> <Byte_D> <Byte_E> <Byte_F> <Byte_Y> <Byte_Z>
where The significant data is Left=ABC, Right=DEF.
Then the EDMA controller will pull off the data and stuff it into the following 16bit PCM format: ABDE
My capture does not produce correct data. Interesting, I can program the McBSP, to caputure 3x24bit words but the second channel is very low. This is because I am getting the following:
<Byte_A> <Byte_B> <ZERO> <Byte_D>: 'AB0D'
I'm able to adjust the gain so that the output is decent but there the resolution is poor on the second channel ( of course, only having 8 bits of data)
Here is the McBSP Regs:
SRGR.CLKSM = 0;
PCR.SCLKME =1
SRGR.FSGM = 1
PCR.CLKRP =1
PCR.FSRP = 1
SPCR.RRST = 0
SPCR.RINTM = 3
SPCR.FREE = 1;
RCR.RFRLEN=1; // 2 data words
RCR.RDATDLY=1; // 1 bit i2s data delay
SRGR.FWID=31; // 32 bit data word
SRGR.FWID = 63; // 64 bit left+right frame ( this is a don't care, since we are using FSR framing, i believe)
RCR.RWDLEN1 = 5; // 32 bit data word ( The define for this is wrong, 5 is 28bits for McASP, but on DM365 5 is 32 bits for McBSP)
dma_params->data_type = 2 ; // feeds into the EDMA DST_BIDX
Given that I have something working with 3x24 bits, but not 2x32 bits, it's got to be a data transforming issue. Understand that the
codec is providing the FSR framing signal and is sending a 32bit left and then 32bit right channel.
Questions:
1. Do the McBSP regs look ok?
2. Is the EDMA messing the data up?
a. How do I program the EDMA to send just block move the data? Here are the EDMA regs for my xfer ( captured in plat-davinci/dma.c):
OPT=0010_3000, A_B_CNT=1000_0004, BIDX=0002_0000 ( Why is SRCBIDX equal to zero).
3. Do you have any suggestions?
I'm using the Montavista kernel ( based on 2.6.18).
Thanks, Brett
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