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No division instructions with AM335x

Andreas Gersbacher
Prodigy 90 points
Other Parts Discussed in Thread: AM3352

Hello,

the AM3352 is a Cortex A8 with ARMv7-A Architecture. This architecture only ".... optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instructions sets, or implemented if the Virtualization Extensions are included" [1]

My question: Does the AM3352 of TI support "virtualization extensions" or is the software library function "__aeabi_idivmod" the only option for division instructions?

Thanks.


[1] http://en.wikipedia.org/wiki/ARM_architecture#Arithmetic_instructions

  • 0
    TI__Guru**** 393215 points
    Hi Andreas,
     
    Quoting from another post:
     
    "....If you look at section B4.1.83, you can find the Instruction Set Attribute Register 0, VMSA. Divide_instrs, bits[27:24] indicates the implemented Divide instructions. Permitted values are:
     
    0b0000 None implemented.
    0b0001 Adds SDIV and UDIV in the Thumb instruction set.
    0b0010 As for 0b0001, and adds SDIV and UDIV in the ARM instruction set.

    Using Code Composer, I connected via JTAG to an AM335x and read back this register: Instruction Set Attribute Register0: 0x00101111 This indicates that SDIV and UDIV are not implemented since bits [27:24] = 0".