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gpmc clock for nand

jags vg
Intellectual 865 points

Hi All,

We are using nand from micron with omap4460 as a boot device.

Nand is connected to gpmc in 8 bit mode and at cs0.

We are planning to port ubuntu 12.04 on our device and our kernel version is 3.10.12

I have configured proper pin mux for gpmc. We are not providing any CS size and base address for cs0 as somewhere on this forum i have read that size doesn't matter in the case of nand like device.

I am getting following log messages.

[ 0.361724] gpmc_l3_clk not enabled
[ 0.361724] gpmc_l3_clk not enabled
[ 0.361724] Division by zero in kernel.
[ 0.361755] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.12-svn113 #1
[ 0.361785] [<c001a960>] (unwind_backtrace+0x0/0xf0) from [<c00173b0>] (show_stack+0x10/0x14)
[ 0.361816] [<c00173b0>] (show_stack+0x10/0x14) from [<c02b3134>] (Ldiv0+0x8/0x10)
[ 0.361846] [<c02b3134>] (Ldiv0+0x8/0x10) from [<c0026424>] (gpmc_calc_divider+0x24/0x40)
[ 0.361846] [<c0026424>] (gpmc_calc_divider+0x24/0x40) from [<c00264a4>] (gpmc_cs_set_timings+0x18/0x474)
[ 0.361877] [<c00264a4>] (gpmc_cs_set_timings+0x18/0x474) from [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4)
[ 0.361907] [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4) from [<c00394a4>] (gpmc_nand_init+0x74/0x1f4)
[ 0.361907] [<c00394a4>] (gpmc_nand_init+0x74/0x1f4) from [<c0876fd8>] (omap4_panda_init+0x3a8/0x444)
[ 0.361938] [<c0876fd8>] (omap4_panda_init+0x3a8/0x444) from [<c086871c>] (customize_machine+0x1c/0x40)
[ 0.361968] [<c086871c>] (customize_machine+0x1c/0x40) from [<c0008764>] (do_one_initcall+0x34/0x164)
[ 0.361999] [<c0008764>] (do_one_initcall+0x34/0x164) from [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8)
[ 0.361999] [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8) from [<c05fc1c0>] (kernel_init+0x8/0xe4)
[ 0.362030] [<c05fc1c0>] (kernel_init+0x8/0xe4) from [<c00132e8>] (ret_from_fork+0x14/0x2c)
[ 0.362060] gpmc_l3_clk not enabled
[ 0.362060] Division by zero in kernel.
[ 0.362060] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.12-svn113 #1
[ 0.362091] [<c001a960>] (unwind_backtrace+0x0/0xf0) from [<c00173b0>] (show_stack+0x10/0x14)
[ 0.362121] [<c00173b0>] (show_stack+0x10/0x14) from [<c02b3134>] (Ldiv0+0x8/0x10)
[ 0.362121] [<c02b3134>] (Ldiv0+0x8/0x10) from [<c00262e8>] (set_gpmc_timing_reg+0x84/0x98)
[ 0.362152] [<c00262e8>] (set_gpmc_timing_reg+0x84/0x98) from [<c00264c8>] (gpmc_cs_set_timings+0x3c/0x474)
[ 0.362152] [<c00264c8>] (gpmc_cs_set_timings+0x3c/0x474) from [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4)
[ 0.362182] [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4) from [<c00394a4>] (gpmc_nand_init+0x74/0x1f4)
[ 0.362213] [<c00394a4>] (gpmc_nand_init+0x74/0x1f4) from [<c0876fd8>] (omap4_panda_init+0x3a8/0x444)
[ 0.362213] [<c0876fd8>] (omap4_panda_init+0x3a8/0x444) from [<c086871c>] (customize_machine+0x1c/0x40)
[ 0.362243] [<c086871c>] (customize_machine+0x1c/0x40) from [<c0008764>] (do_one_initcall+0x34/0x164)
[ 0.362274] [<c0008764>] (do_one_initcall+0x34/0x164) from [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8)
[ 0.362274] [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8) from [<c05fc1c0>] (kernel_init+0x8/0xe4)
[ 0.362304] [<c05fc1c0>] (kernel_init+0x8/0xe4) from [<c00132e8>] (ret_from_fork+0x14/0x2c)
[ 0.362304] gpmc_l3_clk not enabled
[ 0.362335] Division by zero in kernel.
[ 0.362335] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.12-svn113 #1
[ 0.362365] [<c001a960>] (unwind_backtrace+0x0/0xf0) from [<c00173b0>] (show_stack+0x10/0x14)
[ 0.362365] [<c00173b0>] (show_stack+0x10/0x14) from [<c02b3134>] (Ldiv0+0x8/0x10)
[ 0.362396] [<c02b3134>] (Ldiv0+0x8/0x10) from [<c00262e8>] (set_gpmc_timing_reg+0x84/0x98)
[ 0.362396] [<c00262e8>] (set_gpmc_timing_reg+0x84/0x98) from [<c00265c4>] (gpmc_cs_set_timings+0x138/0x474)
[ 0.362426] [<c00265c4>] (gpmc_cs_set_timings+0x138/0x474) from [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4)
[ 0.362457] [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4) from [<c00394a4>] (gpmc_nand_init+0x74/0x1f4)
[ 0.362457] [<c00394a4>] (gpmc_nand_init+0x74/0x1f4) from [<c0876fd8>] (omap4_panda_init+0x3a8/0x444)
[ 0.362487] [<c0876fd8>] (omap4_panda_init+0x3a8/0x444) from [<c086871c>] (customize_machine+0x1c/0x40)
[ 0.362518] [<c086871c>] (customize_machine+0x1c/0x40) from [<c0008764>] (do_one_initcall+0x34/0x164)
[ 0.362518] [<c0008764>] (do_one_initcall+0x34/0x164) from [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8)
[ 0.362548] [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8) from [<c05fc1c0>] (kernel_init+0x8/0xe4)
[ 0.362548] [<c05fc1c0>] (kernel_init+0x8/0xe4) from [<c00132e8>] (ret_from_fork+0x14/0x2c)
[ 0.362579] gpmc_l3_clk not enabled
[ 0.362579] Division by zero in kernel.
[ 0.362579] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.12-svn113 #1
[ 0.362609] [<c001a960>] (unwind_backtrace+0x0/0xf0) from [<c00173b0>] (show_stack+0x10/0x14)
[ 0.362640] [<c00173b0>] (show_stack+0x10/0x14) from [<c02b3134>] (Ldiv0+0x8/0x10)
[ 0.362640] [<c02b3134>] (Ldiv0+0x8/0x10) from [<c00262e8>] (set_gpmc_timing_reg+0x84/0x98)
[ 0.362670] [<c00262e8>] (set_gpmc_timing_reg+0x84/0x98) from [<c002660c>] (gpmc_cs_set_timings+0x180/0x474)
[ 0.362670] [<c002660c>] (gpmc_cs_set_timings+0x180/0x474) from [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4)
[ 0.362701] [<c0039428>] (omap2_nand_gpmc_retime+0xac/0xb4) from [<c00394a4>] (gpmc_nand_init+0x74/0x1f4)
[ 0.362731] [<c00394a4>] (gpmc_nand_init+0x74/0x1f4) from [<c0876fd8>] (omap4_panda_init+0x3a8/0x444)
[ 0.362731] [<c0876fd8>] (omap4_panda_init+0x3a8/0x444) from [<c086871c>] (customize_machine+0x1c/0x40)
[ 0.362762] [<c086871c>] (customize_machine+0x1c/0x40) from [<c0008764>] (do_one_initcall+0x34/0x164)
[ 0.362762] [<c0008764>] (do_one_initcall+0x34/0x164) from [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8)
[ 0.362792] [<c0865b74>] (kernel_init_freeable+0xfc/0x1c8) from [<c05fc1c0>] (kernel_init+0x8/0xe4)
[ 0.362823] [<c05fc1c0>] (kernel_init+0x8/0xe4) from [<c00132e8>] (ret_from_fork+0x14/0x2c)
[ 0.362823] gpmc_l3_clk not enabled
[ 0.362823] Division by zero in kernel.
[ 0.362854] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.12-svn113 #1
[ 0.362854] [<c001a960>] (unwind_backtrace+0x0/0xf0) from [<c00173b0>] (show_stack+0x10/0x14)
[ 0.362884] [<c00173b0>] (show_stack+0x10/0x14) from [<c02b3134>] (Ldiv0+0x8/0x10)

My questions are:

How can i enable gpmc clock ?

gpmc_l3_clk not enabled

above message i am getting from gpmc.c

static unsigned long gpmc_get_fclk_period(void)
{
unsigned long rate = clk_get_rate(gpmc_l3_clk);

if (rate == 0) {
printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
return 0;
}

rate /= 1000;
rate = 1000000000 / rate; /* In picoseconds */

return rate;
}

So, here we are not able to get the clock.

In, arch/arm/mach-omap2/cclock44xx_data.c file, gpmc clock is configured like.

CLK("omap-gpmc",    "fck",          &dummy_ck),

i think we need to write another structrure here instead of dummy_ck.

Could anyone here help me?

 

-------------------------------------------------------------------------------------------------------------------------------------

 

Thanks, 

Jags Gedia

  • 0
    Prodigy 50 points

    Did you ever resolve this issue?  i am fighting the same problem.  I presume the issue is in my device tree but cannot find any help on the matter.

    Cheers

  • 0 in reply to BDavisSwRI
    Intellectual 865 points

    Hi,

    I have enabled the gpmc clock inside the kernel. 

    i am using kernel 3.10.x and processor is omap4460.

    i have made following changes.

    inside arch/arm/mach-omap2/cclock44xx_data.c file:

    DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
    OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
    0x0, NULL);

    and

    CLK(NULL,   "gpmc_ick",         &gpmc_ick,  CK_443X),

    and

    inside arch/arm/mach-omap2/gpmc.c

    gpmc_l3_clk = clk_get(&pdev->dev, "gpmc_ick");    //previously it was fck instead of gpmc_ick

    thanks,

    Jags VG

  • 0 in reply to jags vg
    TI__Mastermind 29520 points

    Hello Jags,

    Yes, your clock configuration is right.


    The GPMC module belong to CD_L3_2 clock domain. The GPMC is clocked by L3_ICLK2 interface clock.

    The register CM_L3_2_GPMC_CLKCTRL manages the GPMC clocks.

    CM_L3_2_GPMC_CLKCTRL[1:0] MODULEMODE - Control the way mandatory clocks are managed.
    Set this bit-field in 0x1: Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state.

    For more additional information about GPMC clock configuration refer to section 3.8.6.2 GPMC Clocks Frequency Scaling Constraints in OMAP4460 TRM.

    Best regards,

    Yanko