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66AK2Hxx EDMA access.

RY9983
Guru 10570 points

Hello,
I would like to confirm about EDMA access on 66AK2Hxx.

I am seeing the Memory map summary of 66AK2Hxx(sprs866e: P93).
It seems that :
 - The EDMA(SoC master) can access only the first 512MB of DDR3B.
 - The EDMA can NOT access all of the DDR3B area(2GB).

Is that right?

Best regards, RY

  • 0
    TI__Guru* 81335 points

    The response from experts to your post may get delayed due to Christmas and New Year Holidays. 

    Kindly bear with us.

    Thanks.

  • 0
    TI__Expert 6815 points

    Yes, that is correct. All SoC masters other than the ARM and C66x CorePacs can only view the first 512MB of DDR3B data space.

    As you can see, the mapping of DDR3A/B for Keystone-II devices is different than Keystone-I. As such, if you have any more questions please feel free to ask.

  • 0 in reply to Aditya
    Guru 10570 points

    Aditya-san,
    May I have once more question?

    I think the DDR3A is more useful than DDR3B to access by both ARM and DSP cores, because it connects to MSM SRAM.
    And, for ARM and other non-core master, it also is supported coherent memory access.
    For DSP CorePac, it can be optimized using ping pong buffer by EDMA.

    How do you intend to use DDR3B 1.5GB area?

    Best regards, RY

  • 0 in reply to RY9983
    TI__Expert 6815 points

    RY-san,

    You are right, DDR3B will not be the first choice for either DSP or ARM due to longer latency of access compared to DDR3A and also because it is non-coherent with the ARM subsystem. It does, however, provide an alternative in cases where DDR3A is being overloaded.

    Hope this answers your question.

  • 0 in reply to Aditya
    Guru 10570 points

    Aditya-san,
    Thanks for your advise !
    Best regards, RY

  • 0 in reply to Aditya
    Prodigy 245 points

    HI, RY-san:

        I have a question to consult you:

        you said that DDR3B is non-coherent with the ARM subsystem. base on this words. I would understand that data in the DDR3B, so I need to maintain coherent, and if data in the DDR3A, I don't need to maintain coherent.

        is my understanding correct?

        

  • 0 in reply to atower geng
    Guru 10570 points

    atower-san,

    Yes, my understanding is same as you.

    Also, you should check below.
    As described in datasheet,
    0x00 8000 0000-0x00 FFFF FFFF does not be maintained coherent.
    0x08 0000 0000-0x09 FFFF FFFF is supported coherent.

    Best regards, RY