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GPMC interface of AM335x use for SRAM

gongchengshi
Intellectual 390 points

I want to use GPMC interface of 3358 to acess FPGA .the FPGA is used as SRAM.Is there a sample application of GPMC for SRAM in StarterWare. Is there a sample application of GPMC for NorFlash in StarterWare.Are there any related function I can use.

  • 0
    TI__Intellectual 1845 points

    Hi xiangtian,

    Currently there is no sample application of GPMC for SRAM or NOR flash
    in StarterWare. You can take a look at the NAND flash Read/Write example
    as reference for usage of GPMC.

    Additionally you can go through the TRM Memory Subsystem chapter for more details
    on GPMC initializations for different device types.

    Regards
    Anant Pai

  • 0 in reply to Anant Pai
    Intellectual 390 points

    Hi:

    Thank you for your reply

    MT29F2G08AB Flash is used in AM335X EVM General Purpose Daughterboard.The NAND flash is address and data lines multiplexed, Why starterware in on NAND initialization program is set to address lines and data lines are Non- Multiplexing? I put the configuration  code in the following :

    NandStatus_t GPMCNANDInit(NandInfo_t *nandInfo)

    GPMCAddrDataMuxProtocolSelect(baseAddr, cs, GPMC_MUXADDDATA_NOMUX);

    #define GPMC_MUXADDDATA_NOMUX                         (0)

    Register information related to the following

     

    If I use this connection Figure 7-3, how can I configure bit[9-8] of this register GPMC_CONFIG1_i ?I think it should be configured as 1h,AAD-multiplexed protocol device.

    If I use this connection Figure 7-4, how can I configure bit[9-8] of this register GPMC_CONFIG1_i ?I think it should be configured as 0h,Non-multiplexed attached device.

    I think the Connection of NAND is used in AM335X EVM General Purpose Daughterboard is Figure 7-5. Why bit [9-8] of register GPMC_CONFIG1_i in the official program is configured to 0? Why???

     

     

  • 0 in reply to gongchengshi
    TI__Intellectual 1845 points

    Hi xiangtian,

    As pointed out by you the connection of NAND on GPEVM AM335x board is same as the figure 7-5 you have shared.

    If you observe closely the address lines of GPMC are not used to access the NAND device, only the data lines are being used. Hence the MUXADDDATA field of GPMCCONFIG1 field is configured as non-multiplexed device.

    It is the requirement of the NAND protocol where in the address, data and command are sent through the same I/O lines and are identifed using ALE, CLE signal pins.

    For more information on NAND access please refer the 9.1.3.3.12 section of
    GPMC chapter in the TRM. Additionally please refer table 9-5 for GPMC pin multiplexng options.

    Regards
    Anant Pai