Strange behavior in nor flash boot

With the emulator, HW initialization is done in the GEL script code. For standalone, the GEL script must be translated to equivalent AIS settings or the GEL script code must be moved to actual code. A certain amount of AIS initialization is required to read the AIS image (eg. init NOR flash access). If the destination is DDR RAM, then DDR RAM access must be initialized.

Norman Wong

 I think there's some improper configration withe DDR2. So I did following

 1) Erase NOR FLASH
 2) Connect the Emulator and save the register values
 3) Modifyint AISgen by refering 2)
 4) Programming the NOR FLASH
 5) NOR FLASH BOOT
 6) EDIT the GEL file by modifying onTarget() function to do nothing about the configuration.
 7) Check the Registers.

 But I couldn't find any differences. -_-;

 What should I do ?

A suggestion. After NOR boot, connect with the emulator without loading an image. See what the ROM bootloader put in DDR. I've never gotten CCSv5 to connect without loading an image. So I can't say how to do that. CCSv3.3 was just a click to do so.

Perhaps the AIS NOR config is not quite right. Compare GEL script NOR settings with the AIS settings. The ROM bootloader may not be reading the NOR flash correctly. When you say the "board works strange", what does that mean? A corrupt AIS image would cause the ROM bootloader to stop.

There may be other HW init that your code is dependent on. I usually move GEL script code to actual code. That way emulator runs are very close to standalone runs.

When you say the "board works strange", what does that mean?

Actually, I checked my board with the RS-422 SDLC communication. (implemented SDLC IP-core in FPGA)

With the same environment, when I connect with the emulator the board works good.

(peer-to-peer communication, when I send "00010100", my board sent me "00010100")

But, the board boots in NOR FLASH mode, my board send me "00018000"

Since you are able to test the FPGA UART, does that mean your code is running successfully from DDR? How is the FPGA connected? EMIF? Initialization for FPGA connection should be moved from the GEL script to the code.