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Using one CPU to simulate SPI EEPROM to download image to C5509A failed

Hi ,

Now I am trying to simulate the SPI EEPROM sequence (24-bits) by one CPU (acts as SPI slave and send data to C5509A after receiving the READ command and address) to download the DSP image. I can download one simple test DSP image which is very small successfully, but I failed to download our formal image which will be bigger and the phenomenon is that the IO4 never sets high after the boot table finished.

So do you have any suggestion on it? Or could you share the boot loader code which is related to SPI EEPROM boot with me?

Thank you very much!

  • William

    C5509A is an older device, so support and responses will likely be limited. I will try to ping previous experts on this device to see if they have any suggestions to offer.

    It would be good to get additional details on your setup. CCS version, flash tools used, size of image working vs not working, custom board vs EVM/DSK (it would be good to test things out on a EVM/DSK).

    Please see if the follow post/discussion provides any pointers

    http://e2e.ti.com/support/dsp/c5000/f/109/t/39444.aspx

    Regards

    Mukul

  • Hi Mukul,

    Thank you very much for your reply. I fixed the issue today.

    The root cause is that I use external SDRAM and the entry point _c_int00 is placed in it. To boot from SPI EEPROM with 24-bits address, we have to connect the boot gpio to 0001b, which the GPIO0 is connected low. And in that case, the EMIF module will be configured as multiplexed HPI port at reset, not the full EMIF mode as expected.

    The solution is to configure the EBSR register to 0x0001 to select full EMIF mode at the boot table.

    The small program I used is to place all the sections in internal RAM, that is why it could work normally.

    Anyway, thank you very much for your support!

    Best regards!

    William

  • Hi William

    Thank you for updating the post with the resolution.

    Regards

    Mukul