Other Parts Discussed in Thread: SYSCONFIG
Hello,
I'm using omap4430 based custom board.
when i'm booting the u-boot, display flickering happens just before the boot logo appears.
i want to remove the flickering completely so that display will show only the boot logo.
see the initDisplay() code of u-boot=>
void initDisplay() {
/* Config gpio 16 in control module */
__raw_writel((__raw_readl(0x4A1001b8) & 0xFFFF0000) | 0x00000003, 0x4A1001b8);
/* config output enable in gpio 16 */
__raw_writel((__raw_readl(0x4a310134) & 0xFFFeFFFF), 0x4a310134);
/* Reset panel through gpio 16*/
__raw_writel((__raw_readl(0x4a31013C) | 0x00010000), 0x4a31013C);
__raw_writel((__raw_readl(0x4a31013C) & 0xFFFeFFFF), 0x4a31013C);
udelay(100);
__raw_writel((__raw_readl(0x4a31013C) | 0x00010000), 0x4a31013C);
/*enabling GPIO_23*/
__raw_writel((__raw_readl(0x4A1001C4) & 0x0000FFFF) | 0x00030000, 0x4A1001C4);
/* config output enable in gpio 23 */
__raw_writel((__raw_readl(0x4a310134) & 0xFF7FFFFF), 0x4a310134);
/* output high to gpio 23*/
__raw_writel((__raw_readl(0x4a31013C) | 0x00800000), 0x4a31013C);
/*gpio_27*/
__raw_writel((__raw_readl(0x4A1001CC) & 0x0000FFFF) | 0x00030000, 0x4A1001CC);
/* config output enable in gpio 27 */
__raw_writel((__raw_readl(0x4a310134) & 0xF7FFFFFF), 0x4a310134);
/* output high to gpio 27*/
__raw_writel((__raw_readl(0x4a31013C) | 0xFFFFFFFF), 0x4a31013C);
__raw_writel((__raw_readl(0x4a31013C) | 0x08000000), 0x4a31013C);
__raw_writel((__raw_readl(0x4a31013C) | 0xFFFFFFFF), 0x4a31013C);
udelay(50);
/*configure FPGA & KCD*/
select_bus(1, CFG_I2C_SPEED);
agln060_init_config();
cyberdisplay_svga_config();
/* VREF to KCD */
i2c_write(0x0F,0x04,1,&val_reg,1);
/* Write DSS config */
__raw_writel(0x00000003, DSS_CONTROL);
/* Enable PLL modules */
__raw_writel(0xa034600a, DSI_CLK_CTRL);
/* Configure PLLs */
__raw_writel(0x1ce25823, DSI_PLL_CONFIGURATION1);
__raw_writel(0x00656008, DSI_PLL_CONFIGURATION2);
__raw_writel(0x00000000, DSI_PLL_CONTROL);
__raw_writel(0x00000001, DSI_PLL_GO);
/* Write DISPC config for channel LCD */
__raw_writel(0x00002015, DISPC_SYSCONFIG);
__raw_writel(0x0012d640, DISPC_IRQENABLE);
__raw_writel(0x00018308, DISPC_CONTROL);
__raw_writel(0x00020004, DISPC_CONFIG);
__raw_writel(0x00FFFFFF, DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
__raw_writel(0x00010004, DISPC_DIVISOR);
__raw_writel(0x00010004, DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
__raw_writel(0x02309545, DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
__raw_writel(0x01700103, DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
__raw_writel(0x0257031f, DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
/* Write DSI1 general config */
__raw_writel(0x00000315, DSI_SYSCONFIG);
__raw_writel(0x0015c000, DSI_IRQENABLE);
__raw_writel(0x00feea98, DSI_CTRL);
/* Configure DSI1 PHY Timings */
__raw_writel(0x7fff7fff, DSI_TIMING1);
__raw_writel(0xffff7fff, DSI_TIMING2);
__raw_writel(0x00170013, DSI_VM_TIMING7);
/* Configure DSI1 Video Mode Timings */
dsi_hbp = dispc_to_dsi_clock((DISPC_HBP-1)+(DISPC_HSW-1), BPP, LANES);
dsi_hfp = dispc_to_dsi_clock((DISPC_HFP-1), BPP, LANES);
dsi_hsa = 0;
dsi_tl = dispc_to_dsi_clock((DISPC_HBP + DISPC_HSW + DISPC_HFP + PANEL_WIDTH), BPP, LANES);
__raw_writel(0xfa20e081, DSI_VM_TIMING1);
__raw_writel(0x04040117, DSI_VM_TIMING2);
__raw_writel(0x08400258, DSI_VM_TIMING3);
/* Configure DSI1 FIFOs */
__raw_writel(0x13121110, DSI_TX_FIFO_VC_SIZE);
__raw_writel(0x13121110, DSI_RX_FIFO_VC_SIZE);
/* Configure DSI1 Complex IO */
__raw_writel(0xffffffff, DSI_COMPLEXIO_IRQ_ENABLE);
__raw_writel(0x6a000a93, DSI_COMPLEXIO_CFG1);
__raw_writel(0x00030000, DSI_COMPLEXIO_CFG2);
/* Configure DSI PHY */
__raw_writel(0x193b192f, DSI_DSIPHY_CFG0);
__raw_writel(0x42091655, DSI_DSIPHY_CFG1);
__raw_writel(0xb8000015, DSI_DSIPHY_CFG2);
/* Configure DSI lanes in control module */
__raw_writel((LANEMASK1 << 24) | 0xf80000, CONTROL_DSIPHY);
/* Get panel out of reset */
enableIF();
/* Configure DSI VC0 as high-speed command mode to start DDR clock */
__raw_writel(0x20808780, DSI_VC_CTRL(0));
__raw_writel(0x000000db, DSI_VC_IRQENABLE(0));
enableVC(0);
__raw_writel(0x7fffffff, DSI_TIMING1);
__raw_writel((val | 0x4), DSI_VC_IRQSTATUS(0));
/* Send null packet through VC0 to start DDR clock */
__raw_writel(0x00000000, DSI_VC_SHORT_PACKET_HEADER(0));
/* Wait for IRQ for long packet transmission confirmation */
for (i = 0; i < 1000; i++) {
u32 val;
val = __raw_readl(DSI_VC_IRQSTATUS(0));
if (val & 0x4) {
__raw_writel((val | 0x4), DSI_VC_IRQSTATUS(0));
break;
}
udelay(100);
}
if(i == 1000) printf("Display error: null packet timed out on vc0\n");
disableVC(0);
disableIF();
chip = 0x0b;
bus = 1;
if((status = select_bus(bus, CFG_I2C_SPEED) != 0)) {
printf("Setting bus[1]: FAILED");
}
if(i2c_probe(chip) != 0) {
printf("status[%s]: Probing 0x0b failed..\n", __func__);
} else {
printf("status[%s]: Probing 0x0b success..\n", __func__);
}
tc358762_write_register_i2c(0x0b, SYSPMCTRL, 2, 0x00000000, 4);
tc358762_write_register_i2c(0x0b, DSI_LANEENABLE, 2, 0x00000007, 4);
tc358762_write_register_i2c(0x0b, DSI_STARTDSI, 2, 0x00000001, 4);
tc358762_write_register_i2c(0x0b, PPI_D0S_ATMR, 2, 0x00000000, 4);
tc358762_write_register_i2c(0x0b, PPI_D1S_ATMR, 2, 0x00000000, 4);
tc358762_write_register_i2c(0x0b, PPI_D0S_CLRSIPOCOUNT, 2, 0x0000000C - 3, 4);
tc358762_write_register_i2c(0x0b, PPI_D1S_CLRSIPOCOUNT, 2, 0x0000000C - 3, 4);
#ifdef VT_GENOFF
tc358762_write_register_i2c(0x0b, 0x0420, 2, 0x00000150, 4);
#else
tc358762_write_register_i2c(0x0b, LCDCTRL, 2, 0x00000152, 4);
tc358762_write_register_i2c(0x0b, HTIMING0, 2, 0x00580080, 4);
tc358762_write_register_i2c(0x0b, HTIMING1, 2, 0x00280320, 4);
tc358762_write_register_i2c(0x0b, VTIMING0, 2, 0x00170004, 4);
tc358762_write_register_i2c(0x0b, VTIMING1, 2, 0x00010258, 4);
tc358762_write_register_i2c(0x0b, VFUEN, 2, 0x00000001, 4);
#endif
tc358762_write_register_i2c(0x0b, PPI_STARTPPI, 2, 0x00000001, 4);
tc358762_write_register_i2c(0x0b, SYSCTRL, 2, 0x00000200, 4);
/*switch On the backlight for boot logo*/
reg= 0x05; val=0x80;
i2c_write(0x38, reg, 1, &val, 1);
if((status = select_bus(0, CFG_I2C_SPEED) != 0)) {
printf("Setting bus[%d]: FAILED", bus);
}
/* Reconfigure DSI1 VC0 as high-speed video mode */
__raw_writel(0x20808790, DSI_VC_CTRL(0));
/* Write Long Packet header */
__raw_writel(((0x00 << 24) | ((PANEL_WIDTH * BPP / 8)<<8)|(0x3E)),DSI_VC_LONG_PACKET_HEADER(0));
for (i=0 ; i < width*height*4; i+=4) {
HEADER_PIXEL(header_data, pixel);
*((unsigned char *)(0x80000000 + i)) = pixel[2];
*((unsigned char *)(0x80000000 + i+1)) = pixel[1];
*((unsigned char *)(0x80000000 + i+2)) = pixel[0];
*((unsigned char *)(0x80000000 + i+3)) = 0x00;
}
/* Configure GFX pipeline */
__raw_writel(0x80000000, DISPC_GFX_BA0);
__raw_writel(0x80000000, DISPC_GFX_BA1);
__raw_writel(0x02000098, DISPC_GFX_ATTRIBUTES);
__raw_writel((((height-1) << 16) | (width-1)), DISPC_GFX_SIZE);
__raw_writel(((((PANEL_HEIGHT-height)/2) << 16) | ((PANEL_WIDTH-width)/2)), DISPC_GFX_POSITION);
/* Enable GFX pipeline */
__raw_writel(__raw_readl(DISPC_GFX_ATTRIBUTES) | 0x1, DISPC_GFX_ATTRIBUTES);
/* Enable manager (LCD ENABLE) */
__raw_writel( __raw_readl(DISPC_CONTROL) | 0x1, DISPC_CONTROL);
/* De-assert FORCE_TX_STOP_MODE_IO for video mode to work properly */
__raw_writel(0x7fff7fff, DSI_TIMING1);
/* Set GOLCD to sync pipelines */
__raw_writel(__raw_readl(DISPC_CONTROL) | 0x3d, DISPC_CONTROL);
enableVC(0);
enableIF();
}
Plz help me out.
It would be a great help.
Regards
-Kaushal
