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keystone SRIO physical loopback connection evm6678L

Lukasz Mitrega
Intellectual 315 points
Other Parts Discussed in Thread: TMS320C6671

Hello All,

I'm trying to use the SRIO module in the keystone 667x devices. The target platform is a custom design where a TMS320C6671 DSP is connected using 4 SRIO lanes with a Xilinx artix FPGA. Because I'm not familiar with serial rapid IO connections I wanted first to write some codes and test them on the TMDSEVM6678L EVM (the SRIO module is the same in the 6671 and 6678 DSP).

First thing we did was a connection between the TX and RX on SRIO lane 0 on the AMC edge connector (on the evaluation module).

Using this hardware I wanted to realize a physical external loopback on lane 0.

Question 1.
First of all I want to ask if the idea with connecting the RX and TX differential pairs from the SERDES0 is reasonable? And also if such a connection allows to build and test correct SRIO application code?

I'm already trying to build and run a working code on this hardware (EVM with tx rx connection).

First thing that is done is enabling the SRIO blocks. Then is the PLL configuration. I'm getting the PLL lock and then I enable the TX and RX for channel 0 to run in normal operation mode. The default configuration is 4x x1 port so after setting the BOOTCOMPLETE bit I'm checking the SP0_ERR_STAT and LANE0_STAT0 also the SRIO_SERDES_STS register. There are two different behaviors I observed:

1. While configuring the PLL and trying to run some reasonable speeds I got the Port OK bit (SP0_ERR_STAT) together with the RX_SYNC bit (LANE0_STAT0) only if I set the lowest multiplier and quarter rate. But once I read those values () I observe that the port OK bit and rx sync bit are getting 0 after short time.

2. In case of bypassing the PLL (value 11(b) in the CLKBYP field in the serdes macro configuration register) once achieved PORT_OK stays forever. (from this observation I assume that some part of the configuration is OK)

Question 2.
In this case I want to ask if this situation point to some wrong register configuration of the SerDes, Tx, Rx (In this case if there are some recommended values for such a solution) or the whole concept is wrong (Question 1)?

  • 0
    TI__Mastermind 23525 points

    Are you using the PDK example to show you how to do the configuration?

    http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html

    Then look at: C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\srio\example\SRIOLoopbackDioIsr

    This thread discusses how to take it out of loopback and put in normal mode, which would allow external loopback:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/170264/752157.aspx#752157

    Yes, you can loopback port 0 TX to RX.

    Regards,

    Travis

  • 0 in reply to tscheck
    Intellectual 315 points

    Hi,

    thanks for the tip.

    I'll report the result from the PDK example as soon as I integrate it with my code.

    Regards,

    Lukasz

  • 0 in reply to Lukasz Mitrega
    Intellectual 315 points

    Hello again,

    I tested the example project (SRIO_LoopbackDioIsrexampleproject). However my results were not as I accepted.

    The physical loopback was realized on the 6678 EVM edge connector. Two ports were looped. One with very short cable (obout 2 mm - shortest possible connection for proper pins on the edge connector) and one with about 2 cm cables soldered to the connector.

    I changed the example codes to set the lanes in normal mode. I was able to get "port ok" status and to transmit the data through the physical loopback on the port with shortest possible  cable (I wasn't changing the Rx and Tx configuration, small code changes were needed to use other ports than 0 to perform DIO operations but its unimportant for this case). I also wanted to run the loopback using the port with 2cm cables on loopback. But I was not able to get stable "Port OK". I mean that the port ok bit changes all the time (appears to be 1 but after a while it changes back to 0 and than again to 1). I modified the code only to examine the "Port OK" status and tried to change the connection parameters (Tx, Rx, PLL) but I did't get a stable "Port Ok".

    My goal (after successful realizing the physical loopback) was to connect the 6678 EVM to an evaluation module with virtex6 fpga to set a srio connection. We tested the physical loopback on the fpga evaluation board and we got a port ok and stable link using long cables. I thought that there is no point to connect those evaluation boards (fpga and dsp) when I can't configure the dsp to run a loopback connection using longer cables. Its a little bit strange, because the physical loopback using the fpga was stable using very poor cables connection.

    In this situation I want to ask a question.

    Are my problems with setting up the connection on the port with 2cm cables loopback normal? Is there a way to configure the transmitter and receiver to allow a connection on this configuration? Or shall I stop using the physical loopback and try to connect the 6678 EVM with the fpga board?

  • 0 in reply to Lukasz Mitrega
    TI__Mastermind 23525 points

    You can not simply solder wires to the AMC connector edge and expect these Gb/s links to function.  This is not supported since signal integrity  with match impedance differential pairs is needed.  Any type of impedance mismatch or signal reflections can cause SerDes based interfaces to not work.  You can use a breakout card to connect multiple EVMs or an EVM with the FPGA EVM.  See:

    https://estore.ti.com/CI2EVMBOC--P2685.aspx

    or

    something like this adapter to convert from the AMC connector to SMA cables:

    http://silicontkx.com/SMA-AMCULTRA9000.html

    I'd also suggest you take a look at this thread regarding Port_OK:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/196080/850001.aspx#850001

    Regards,

    Travis

  • 0 in reply to tscheck
    Intellectual 315 points

    Just to confirm. We have our custom design with TMS320C6671 and Xilinx Artix Fpga. The Srio connection supports signal integrity and there are no problems with Port OK.

    Thanks for tips.

  • 0 in reply to Lukasz Mitrega
    TI__Mastermind 23525 points

    That's great news.

    Regards,

    Travis