The DM365 gel file from Spectrum has the following sequence of instructions:
*SDCFG1 = 0x0853C832;
*SDREF = 0x00000768; // Program SDRAM Refresh Control Register
*VBUSMP = 0x000000FE; // VBUSM Burst Priority Register, pr_old_count = 0xFE
*SDTIM0 = 0x3C934B51; // Program SDRAM Timing Control Register1
*SDTIM1 = 0x4221C722; // Program SDRAM Timing Control Register2
*SDCFG1 = 0x08534832; // Program SDRAM Bank Config Register
The SDCFG1 setting appears to try to write a '1' to DDR_DDQS to enable differntial DQS but it doesn't work since hte BOOTUNLOCK bit is a '0'.
This appears to be wrong since I guess we would prefer differential DQS since we do have both DQS and DSQN connected.
Is that correct?
My customer noticed the following on their board:
They chose to not use serial terminations on the DDR signals. The documentation says that:
When no termination is used on data lines (0 Ωs), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.
On their test board, without making any changes to drive strength they found the interface works but they saw over- and undershooting data signals during READ operations, but not during WRITE operations. When they changed bit 18 in SDCR (DDRDRIVEEN) then the overshooting and undershooting during READ went away, as expected. But then WRITE signals are more or less unchanged. They run the VTP calibration from the GEL file in both cases. Why is this? Does this have anything to do with VTP calibration? Is it possible, that the VTP calibration sets automatically driver strength and impedance for the DM365 ? Rgds -Dipa-
