when i configure L3 as data memory,the cpu access to L3 is stalled.
Hereafter,I setup L3 as cacheable,it works well.
so anybody can tell me why this happen?
Jasonzhou,
Welcome to the TI E2E forum. I hope you will find many good answers here.
In addition you can find some details through the TI.com documents and the TI Wiki Pages.
Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.
A cache-based memory system, multiple copies of the same memory location may exist simultaneously, a protocol must be followed that ensures that requestors do not access an out-of-date copy of a memory location.
Since cache cannot be used for code or data placement by the linker, all sections must be linked into SRAM or external memory.
Please see the wiki articles, this will give more details of cache memory.
http://processors.wiki.ti.com/index.php/Cache_Management
http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache
http://processors.wiki.ti.com/index.php/Cache_Visualization
