• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 98 subscribers
  • Views 997 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM8148 DDR3 Timings

Elad Roichman
Intellectual 350 points

Hello,

I'm wroking on my own EVB with DM8148 SoC on it. The chip is connected to DDR parts which are the same parts as in the DM8148 TI Evaluation board. These DDRs are: MT41J128M8JP-125 1Gb_DDR3 manufactured by Micron.

Our DDR clock is 533 MHz (OPP166).

We asked TI for the DDR registers configuration in the C674x DSP (which are initialized during hte U-boot process) and received the attached gel file.

However, looking at the registers and comparing them to the DDR specifications, I found some mismatches between the required settings and TI's configuration. Mismatches include the following:

1) T_RAS - configured to be 35.6ns (TI) while the minimum allowed is 37.5ns (DDR spec)

2) T_RC - configured to be 48.75ns (TI) while the minimum allowed is 52,5ns (DDR spec)

3) T_XSNR - configured to be 120ns (TI) while the minimum allowed is 120.625ns (DDR spec)

4) T_RAS_MAX - configured to be 15 (TI) instead of 9 (DDR spec)

These timers can be critical to proper operation of the DDR.

I wanted to ask if there are any special reasons for the mismatches? Or is it something that should be fixed?

Please reply ASAP as we're in the middle of a bringup procedure to this board.

Thanks in advance,

Elad Roichman.

DM8148_EVM.GEL
  • 0
    TI__Guru**** 170625 points

    Hi Elad,

    I am working with EZSDK 5.05.02.00 / PSP 04.04.00.01, and we have the below DM8148 EVM GEL file:

    ti-ezsdk_dm814x-evm_5_05_02_00/board-support/host-tools/DM814x_gel.zip/DM814x_PG2.x.gel file. Is this DM814x_PG2.x.gel file the same as your DM8148_EVM.gel (regarding DDR3 settings)?

    Also, have you gone through the below user guide?

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

    8863.DM814x_PG2.x.gel

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 350 points

    Hi Pavel,

    Your gel file isn't the same one. My gel file (which I attached to my original post) is newer.

    As I wrote in my post, the problem is only with four DDR3 timing settings: T_RAS, T_RC, T_XSNR and T_RAS_MAX. The rest of the configuration seems to match the DDR specifications.

    My question is: What's the reason for the mismatches? Is it a bug? Or something that was taken into consideration?

    I forgot to mention that the board is up and running. I just want to make sure that the DDR3 settings in the C674x DSP are correct and according to the DDR3 memory part specifications (assuming that the same DDR3 parts are being used).

    I can't rely on my working EVB as a proof that the DDR3 configuration is correct.

    This issue was raised in order to avoid future problems with customers in which the DDR3 interface will misbehave because of these configuration mismatches.

    Regards,

    Elad.

  • 0
    TI__Guru**** 170625 points

    Elad,

    Elad Roichman said:
    However, looking at the registers and comparing them to the DDR specifications, I found some mismatches between the required settings and TI's configuration.

    Which registers exactly do you refer? Please provide me a list, I will compare the settings from the GEL file with the u-boot source code. By "DDR specifications" do you mean the Micron DDR3 datasheet?

    Best regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 350 points

    Hi Pavel,

    The problematic registers are: SDRAM Timing 1 Register (SDRTIM1), SDRAM Timing 2 Register (SDRTIM2) and SDRAM Timing 3 Register (SDRTIM3).

    By "DDR specifications" I meant the Micron DDR3 datasheet.

    Thanks in advance,

    Elad.

  • 0 in reply to Elad Roichman
    TI__Guru**** 170625 points

    Elad,

    These SDRAM timing registers (from the DM8148_EVM.gel file) are aligned with the values described in TI814x GEL file from:

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

    To verify you DDR timing parameters, you can use the below spreadsheet:

    http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot#Overview

    Configure the DDR controller (Also referred as EMIF) with the timing parameters calculated from the spreadsheet File:DM814x DDR Controller Register Configuration spreadsheet v1.0.zip based on the timing parameters mentioned in the data sheet of the specific DDR device being used.

    You can also find info regarding DDR timing in below links:

    http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips#AC_timing_registers

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/271945.aspx

    Regards,
    Pavel