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Set McASP0 in master mode to generate frame clock and bit clock

Shabbir Limdiwala
Expert 2060 points

Hi,

We have custom board designed by taking AM335x sitara Soc as a reference. We have used si3050+si3019 chip for developing POTS.

We have connected si3050 to SPI0 for control and McASP0 for data transfer.

I took reference of audio codec chip which connected to I2c1+McASP1. Here i found that audio codec chip generates frame clock and bit clock.

But in our case we want McASP0 controller to generate frame clock and bit clock.

So is it possible to generate these clocks from McASP0 ? and if yes then what changes we need to make in
sound/soc/davinci/davinci-mcasp.c and sound/soc/davinci/davinci-mcasp.c ?


Seeking quick response.


Thanks in advance,

Shabbir Limdiwala

  • 0
    TI__Guru**** 393215 points

    Hi Shabbir,

    Yes, this is possible. I'm not a software expert, so cannot say exactly what changes you willl need to make in the source files, but you will need definitely to change the pinmux for the two clocks - make them outputs with receiver enabled. For clock frequency setting please refer to the AM335X Technical Refernce Manual, Rev. J, section 22.3.5.

  • 0 in reply to Biser Gatchev-XID
    Expert 2060 points

    Hi,

    I want to generate exact 256KHz Bit clock and 8 KHz frame clock. In my case AUXCLK is 24MHz. I have tried generating these clocks by modifying AHLKXCTL and ACLKXCTL registers as mention in section 22.3.5 Figure 22-17. But I couldn't able to get exact clocks by dividing AUXCLK.

    Is there any way to change AUXCLK ? If no, is there any other way to get exact Bit clock and frame clock ?

    Thanks and Regards,

    Shabbir Limdiwala

  • 0 in reply to Shabbir Limdiwala
    TI__Guru**** 393215 points
    AUXCLK is the main oscillator clock. There is no way to change it. The other way would be to use the mixed mode - an external high-frequency clock is input to the McASP on either the AHCLKX or AHCLKR pins, and divided down to produce the bit rate clock.