Dear TI e2e community members,
What I have achieved so far:
Currently i am working on a piece of software which has to be deployed on the OMAP4460 SoC. The functionality of the software is very simple: It has to read data from a set of sensors via the I2C4 bus, process the data and then write to a set of actuators via the I2C4 bus. This has to be done 100 times per second (100Hz). I already have deployed this piece of software on the Cortex-M3 subsystem and is working just fine. Note that when reading/writing to the I2C4 bus (or any other peripheral device), both the L3 interconnect and the L4 peripheral interconnect is used in order to reach the I2C4 module.
The challenge:
Currently only the just described piece of software is deployed on the OMAP4460 and now I want to deploy other pieces of software on the MPU subsystem (the subsystem with the A9 CPUs). Possibly also other subsystems (except for the Cortex-M3 subsystem), like the SGX540 and IVAHD subsystem, will be used for hardware accelerated stuff. As a result, there will be a lot of additional traffic on the L3 interconnect.
Assumption:
To make things easier I wont allow the other pieces of software to use any peripheral device. I.e. the L4 peripheral interconnect will only be used by the piece of software running on the Cortex-M3 subsystem.
Question:
How can I guarantee that the other pieces of software I want to deploy on the MPU subsystem do not interfere with the read/write transactions between the Cortex-M3 subsystem and the I2C4 module connected to the L4 peripheral interconnect? If it is not possible to guarantee NO interference, how can I bound the amount of the interference?
Any suggestions or hints will be appreciated.
Kind regards,
Richard van Berkel
