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GPMC access?

Other Parts Discussed in Thread: AM3874

Hi,

I have one question for DUCATI(=M3) access.

Sympton:

Now my customer connects ASIC to GPMC module of AM3874.

Please see the assembler list in the below.

1)    If data 0x02(R4) is written to physical address 0x481800574, MODULEMODE of DUCATI_CLKCTRL Registeris enabled.

2)    When DUCATI(=M3) is enabled, wrong access to the outside of M3 happens, and its address is output from GPMC external bus to customer's  ASIC.

3)    If ASIC can’t respond to wrong address on GPMCexternal bus, GPMC module continues to wait the readysignal from ASIC. According to the analysis, the read access to 0x84413A0 and 0x8641320 happens. And this wrong accrss causes this failure.

4)    If Cortex-A8 core access to GPMC when GPMC contunes to wait the ready signal, GPMC does not respond to A8 core, and data abort happens. This is one prediction.

 

0x80008adc  E5903B10       LDR          R3,[R0,#0xb10]    

0x80008ae0  E3A04002       MOV          R4,#0x2

0x80008ae4  E7C4321F       BFC          R3,#4,#4

0x80008ae8  E5803B10       STR          R3,[R0,#0xb10]

0x80008aec  E5903B10       LDR          R3,[R0,#0xb10]

0x80008af0  E7C4311F       BFC          R3,#2,#4

0x80008af4  E5803B10       STR          R3,[R0,#0xb10]

0x80008af8  E5804518       STR          R4,[R0,#0x518]   

0x80008afc  E5804574       STR          R4,[R0,#0x574]    <-------

0x80008b00  E5903574       LDR          R3,[R0,#0x574]

0x80008b04  E3130803       TST          R3,#0x30000

0x80008b08  1AFFFFFC       BNE          0x80008b00

R0 virtual address : 0x90180000、R0 physical address : 0x48180000

Questions:

1) I think that red character line enables the DUCATI(=M3) . Is my understanding right?

2)If the red character line is execulted, some GPMC access happens to the external bus?

I can't understand why some GPMC access happens by executing the red character line.

Please advise me.

Best regards,

Michi   

 

  • Hi Michi,

    Michi Yama said:
    2)    When DUCATI(=M3) is enabled, wrong access to the outside of M3 happens, and its address is output from GPMC external bus to customer's  ASIC.

    Do you mean that when enable M3, the M3 is trying to access the GPMC?

    Cortex-M3 ARM can not access GPMC directly, the access should go through the M3 L2 MMU. Thus you need to check if the L2 MMU registers are configured correctly.

    Best regards,
    Pavel

  • Dear Pavel-san,

    Thank you for your quick reply.

    We tested to reset M3 by using DUCATI_M3_RST1/2 bit of RM_DEFAULT_RSTCTRL register. Please see the below.

    bit3:                                bit2:
    <DUCATI_M3_RST2>     <DUCATI_M3_RST1>     <Strange GPMC access>
    0                                     0                                       Happened
    0                                     1                                       Happened
    1                                     0                                       Happened
    1                                     1                                       Not Happened
    How do you judge the test result?
    Please advise me again.
     
    Best regards,
    Michi
     
  • Michi,

    I think you should be aligned with the M3 Power-On Reset Sequence and/or warm reset sequence. We have some specific requirements after enabling the M3. See AM387x TRM, sections 2.7.25 Media Controller Power-On Reset Sequence and 2.7.26 Media Controller Warm Reset Sequence.

    Best regards,
    Pavel

  • Dear Pavel-san,

    Thank you for your support.

    We found some wrong code in ADENEO BSP. Now we are asking its code to ADENEO.

    Best regards,

    Michi