I'm also trying to characterize the context switch latency into my ISR and I see in the disassembly the MMAP qualifier. I see this is needed when trying to access memory mapped location as opposed to a data-memory location.
For example: "AND #63775,mmap(@ST1_55)"
Assuming the AND instruction takes 1 cycle and the mmap instruction takes 1 cycle, does this instruction take 2 cycles to execute? Or, are the instructions done in parallel?
I'm basically trying to determine if I need to add another cycle to my calculation each time I see the mmap qualifier, whether its associated with PSH, AND, OR, etc.
Thanks,
Adam