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The tested speed of srio in 1.25Gbps is larger than the theory speed, but in the 2.5Gbps and 3.152Gbps is right

Dear TI,

I am facing a problem when I test the bandwidth of srio DirectIO of c6455. The board is custom designed which has two c6455 on it. The RIOCLK is 125M, when I test the 2.5Gbps and 3.125Gbps, I used the MPY 10x and 12.5x mode respectively, and the practical bandwidth I got is 1.85Gbps and 2.24Gbps respectively and I think the result is correct. But when I test the 1.25Gbps, I used the MPY 5x mode RATE is full or the MPY 10x mode RATE is half, is result is 1.7Gbps, it’s not correct. So where is problem, and how to get the right bandwidth in 1.25G mode?

And another question, the RIOCLK is 125M, I made the MPY is 8x and RATE is full, the srio can still transmit data, so can I get the conclusion that any MPY in the below can work in c6455?

Thank you very much

Best wishes

  • Jamse,

    It may not be likely for someone to guess what the mistake is in your setup or measurement or board. The best information will come from connecting test equipment to the SRIO pins to observe the actual rate of data being transmitted. In this way, you can clearly determine what rate is implemented on the pins and then back up from there to determine what is the issue in the other parts of your system.

    Regards,
    RandyP