Hi,
I'm trying to configure McBsp to work in slave mode with aic23 chip.
using the basic example DXR<->DRR it works great, loopback, or wave generation
//poll receiver is ready
while(CSL_FEXT(mcbspRegs->SPCR,MCBSP_SPCR_RRDY)
!= CSL_MCBSP_SPCR_RRDY_YES);
//read receive register
data = mcbspRegs->DRR;
//poll transmitter ready
while(CSL_FEXT(mcbspRegs->SPCR,MCBSP_SPCR_XRDY)
!= CSL_MCBSP_SPCR_XRDY_YES);
//write to transmit register
mcbspRegs->DXR = data;
The problem accoures when I'm trying to work with psp drivers, nothing works, in some tests I get non relevant data or my data don't reach the endpoint. event though I get interrupt after GIO_Submit.
There are also cases in which I get at the DX output a sinus wave I didn't send, even when i send an empty buffer. I made sure that the McBsp registers are configured as I want them to.
Maybe it is my configurations, how can I configure the mcbsp to send 32bit data every frame using EDMA with psp drivers. I use PSP 1_10_03.
Here is part of my example:
#pragma DATA_ALIGN(mcbspRBuffer, 32);
Uint8 mcbspRBuffer[TEST_BUFFER_LENGTH] = {0}; // input buffer
#pragma DATA_ALIGN(mcbspWBuffer, 32);
Uint8 mcbspWBuffer[TEST_BUFFER_LENGTH] = {0}; // output buffer
PSP_mcbspHwCfgRaw mcbspRawHwCfg = {
/**< Serial Port Control Register */
CSL_FMKT(MCBSP_SPCR_DLB, DISABLE) // disable loopback mode
| CSL_FMKT(MCBSP_SPCR_FREE, DISABLE) // debugger
| CSL_FMKT(MCBSP_SPCR_SOFT, ENABLE) // debugger
| CSL_FMKT(MCBSP_SPCR_FRST, RESET)
| CSL_FMKT(MCBSP_SPCR_GRST, RESET)
| CSL_FMKT(MCBSP_SPCR_XINTM, XRDY)
| CSL_FMKT(MCBSP_SPCR_XSYNCERR, NO) // no sync error is detected
| CSL_FMKT(MCBSP_SPCR_XRST , DISABLE)
| CSL_FMKT(MCBSP_SPCR_RJUST, RSE) // right justify zero fill MSB in DRR;
| CSL_FMKT(MCBSP_SPCR_CLKSTP, DISABLE_00) // not spi mode
| CSL_FMKT(MCBSP_SPCR_DXENA, OFF) // Ask Ariel
| CSL_FMKT(MCBSP_SPCR_RINTM, RRDY) // rx interrupt
| CSL_FMKT(MCBSP_SPCR_RSYNCERR, NO) // no sync error is detected
| CSL_FMKT(MCBSP_SPCR_RRST, DISABLE)
,
/**< Receive Control Register */
CSL_FMKT(MCBSP_RCR_RPHASE, SINGLE_FRM) // single frame
| CSL_FMKT(MCBSP_RCR_RCOMPAND, MSB) // ???
| CSL_FMKT(MCBSP_RCR_RFIG, YES) // ???
| CSL_FMKT(MCBSP_RCR_RDATDLY, 0BIT) // Receive delay bit
| CSL_FMK (MCBSP_RCR_RFRLEN1, 0) // one word in phase 1
| CSL_FMKT(MCBSP_RCR_RWDLEN1, 32BIT) // receive word 16bit
| CSL_FMK (MCBSP_RCR_RFRLEN2, 0) // one word in phase 1
| CSL_FMKT(MCBSP_RCR_RWDLEN2, 32BIT) // receive word 16bit
| CSL_FMKT(MCBSP_RCR_RWDREVRS, DISABLED) // Receive 32-bit bit reversal enable bit.
,
/**< Transmit Control Register */
CSL_FMKT(MCBSP_XCR_XPHASE, SINGLE_FRM) // single frame
| CSL_FMKT(MCBSP_XCR_XCOMPAND, MSB) // ???
| CSL_FMKT(MCBSP_XCR_XFIG, YES) // ???
| CSL_FMKT(MCBSP_XCR_XDATDLY, 0BIT) // Receive delay bit
| CSL_FMK (MCBSP_XCR_XFRLEN1, 0) // one word in phase 1
| CSL_FMKT(MCBSP_XCR_XWDLEN1, 32BIT) // receive word 16bit
| CSL_FMK (MCBSP_XCR_XFRLEN2, 0) // one word in phase 1
| CSL_FMKT(MCBSP_XCR_XWDLEN2, 32BIT) // receive word 16bit
| CSL_FMKT(MCBSP_XCR_XWDREVRS, DISABLED) // Receive 32-bit bit reversal enable bit.
,
/**< Sample Rate Generator Register */
CSL_FMKT(MCBSP_SRGR_GSYNC, SYNC) // Sample-rate generator clock synchronization bit is only used when the external clock (CLKS)
| CSL_FMKT(MCBSP_SRGR_CLKSP, RISING)
| CSL_FMKT(MCBSP_SRGR_CLKSM, INTERNAL) // Sample rate generator input clock mode bit.
| CSL_FMKT(MCBSP_SRGR_FSGM, FSG) // Sample-rate generator transmit frame-synchronization mode bit is only used when FSXM = 1 in PCR.
| CSL_FMK (MCBSP_SRGR_FPER, 1500) // frame period
| CSL_FMK (MCBSP_SRGR_FWID, 0) // frame width
| CSL_FMK (MCBSP_SRGR_CLKGDV, 0) // clock divider value // clock divider value, smallest divider
,
/**< Pin Control Register */
CSL_FMKT(MCBSP_PCR_FSXM, EXTERNAL) // internal frame sync EXTERNAL
| CSL_FMKT(MCBSP_PCR_FSRM, EXTERNAL) // internal fram sync
| CSL_FMKT(MCBSP_PCR_CLKXM, INPUT) // trans clock mode
| CSL_FMKT(MCBSP_PCR_CLKRM, INPUT) // trans clock mode
| CSL_FMKT(MCBSP_PCR_SCLKME, BCLK) // trans clock mode
| CSL_FMKT(MCBSP_PCR_FSXP, ACTIVEHIGH) // trans clock mode
| CSL_FMKT(MCBSP_PCR_FSRP, ACTIVEHIGH) // trans clock mode
| CSL_FMKT(MCBSP_PCR_CLKXP, FALLING) // trans clock mode
| CSL_FMKT(MCBSP_PCR_CLKRP, FALLING) // trans clock mode
};
mcbspChanParams.userLoopJobBuffer = NULL;
mcbspChanParams.userLoopJobLength = 0;
mcbspChanParams.edmaHandle = hEdma;
mcbspChanParams.noOfTdmChans = 1;
mcbspChanParams.wordWidth = PSP_MCBSP_WORDLEN_32;
mcbspChanParams.intrNum = 48u;
GIO_Attrs gioAttrs = GIO_ATTRS;
mcbspHandleOut = GIO_create("/MCBSP0", IOM_OUTPUT, NULL, &mcbspChanParams, &gioAttrs);
mcbspHandleIn = GIO_create("/MCBSP0", IOM_INPUT, NULL, &mcbspChanParams, &gioAttrs);
void mcBsp_edma_loopback()
{
Int status = 0;
PSP_mcbspTransParam ioBuffer = {0};
size_t bufLen = TEST_BUFFER_LENGTH;
Uint32 errCounter = 1;
// set buffers
ioBuffer.transAddr = (Uint8*)&mcbspRBuffer[0];
ioBuffer.receiveAddr = (Uint8*)&mcbspRBuffer[0];
while(1)// test loop
{
#ifdef MCBSP_ASYNC
// read data Interrupt
status = GIO_submit(mcbspHandleIn, IOM_READ, &ioBuffer, &bufLen, &mcBspRxAppCb);
mcBspRxCount++;
#else
// read data Polling
status = GIO_submit(mcbspHandleIn, IOM_READ, &ioBuffer, &bufLen, NULL);
#endif
// check status
if (status < 0)
{
errCounter++;
if((errCounter % 100) == 0)
{
printf("\r\nBIOS McBSP0:Error in sample Test \n");
break;
}
continue;
}
#ifdef MCBSP_ASYNC
// wait for callback
while(mcBspRxCbCount < mcBspRxCount)
{;}
#endif
#ifdef MCBSP_ASYNC
// write data (interrupt)
status = GIO_submit(mcbspHandleOut, IOM_WRITE, &ioBuffer, &bufLen, &mcBspTxAppCb);
mcBspTxCount++;
#else
// write data (polling)
status = GIO_submit(mcbspHandleOut, IOM_WRITE, &ioBuffer, &bufLen, NULL);
#endif // MCBSP_ASYNC
// check status
if (status < 0)
{
errCounter++;
if((errCounter % 100) == 0)
{
printf("\r\nBIOS McBSP0:Error in sample Test \n");
break;
}
continue;
}
#ifdef MCBSP_ASYNC
// wait for callback
while(mcBspTxCbCount < mcBspTxCount)
{;}
#endif
} // while
}
