why need to configure the cache before DDR3 initialization?

Hi all,

I am testing the DDR3 in our board using the Keystone DDR3 init example code.

In this example, there are some codes before the ddr3 initialization like

CODE1:

int i;

CACHE_setL1PSize(CACHE_L1_32KCACHE);
CACHE_setL1DSize(CACHE_L1_32KCACHE);
CACHE_setL2Size(CACHE_1024KCACHE);
CACHE_invAllL1p(CACHE_WAIT);
CACHE_wbInvAllL1d(CACHE_WAIT);
CACHE_wbInvAllL2(CACHE_WAIT);

/*make other cores local memory cacheable and prefetchable*/
for(i=16; i<24; i++)
        CGEM_regs->MAR[i]=1|(1<<CSL_CGEM_MAR0_PFX_SHIFT);
/*make DDR cacheable and prefetchable*/
for(i=128; i<256; i++)
        CGEM_regs->MAR[i]=1|(1<<CSL_CGEM_MAR0_PFX_SHIFT);
/*make other space non-cacheable and non-prefetchable*/
for(i=24; i<128; i++)
	CGEM_regs->MAR[i]=0;

Then there are the DDR3 initialization codes like
CODE2:

KeyStone_main_PLL_init(624,31);
KeyStone_DDR_PLL_init (79, 2);
TCI6618_EVM_DDR_Init(666.667); 	

After these, I can write or read the DDR3 sdram.

What confuses me is that why need these CODE1 before DDR3 initializtion CODE2.
If I delete the CODE1, I can not w/r the DDR3 correctly.
Can anyone tell me why? Or tell me read which docs.

Thanks a lot!