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TMS320C6678 Reference Clocks

Tom Saluzzo
Expert 1280 points
Other Parts Discussed in Thread: CDCE62005

On page 40 of the SPRABI2C Design guide TI recommends 66.667Mhz for the DDR clock, but allows 40Mhz to 312.5 Mhz. We plan on using 100Mhz for the DDR clock, so we can provide all the reference clocks with only one CDCE62005 clock generator.

There is an internal DDR clock PLL that will allow us to get 66.667Mhz from the 100Mhz reference. I wanted to know why they recommend using 66.667Mhz for the DDR clock. We also plan to use the core clock for the PASS clock reference VIA the internal multiplexer. What is the disadvantage to this?

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    TI__Mastermind 46460 points

    Tom S,

    There is no downside to your system design.  100MHz is equally valid for the DDR reference clock.  The internal PLL can generate the optimum DDR3 frequencies from both.

    Use of the internal mux for the PASS PLL input clock is also fully acceptable assuming you are using 100MHz for the reference clock into the core clock PLL.  Separate PASS PLL clock is needed if the core clock reference is an odd rate such as 122.88MHz.

    Tom J