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On-chip memory: is it enough for the User's program code?

joe lindula
Mastermind 6930 points

Hello, I'm looking at the C667x and C665x families and have a question about the L1 and L2 cache. Do these families have enough L1 and L2 memory to store the User's program code? Can the program code be loaded into the MSM SRAM? 

 

Thanks,

joe

  • 0
    TI__Mastermind 30825 points

    It's unlikely that the full program code would reside in the L1P memory (or cache if in cache mode) given that it's only 32KB per core.

    Depending on the size of program it may be able to reside in L2 Memory of the CorePacs, which is 512KB or 1MB depending on the device, or possibly in MSMC which as 4MB of MSMC on the C667x device and 1MB of MSMC in the C665x devices.

    It is really going to depend upon the code as to whether or not this is sufficient to hold everything.  Some very specific task oriented items may hold everything, while larger scale in terms of providing lots of various functionality are going to have a lot more routines and consume a lot more program space.

    Details regarding how much memory is available for each of the devices are available on their product pages, and in their data manuals which are also on their product pages.

    Best Regards,

    Chad