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SMPTE 296

Vaishak R
Intellectual 495 points
Other Parts Discussed in Thread: OMAPL138

Hi,

I trying to interface omnivision sensor configured to generate 720p format frame at 30 frames per second with 48Mhz input to VP_CLKin0 & CLKIN1.

Can somebody specify the maximum input clock that needs to be given to VP_CLKin0 & CLKIN1 to capture 720p format frame in OMAPL13X

  • 0
    TI__Expert 4760 points

    Hi Vaishak,

    The SMPTE 296 M mode requires the same clock control for the VPIF module as in BT.656 and BT.1120modes. The video input clock source is 74.25 MHZ.

    Please refer Table 36-8 page no 1766 in the Technical reference manual for the register configuration on SMPTE 296M Input/Output.

    you need to operate the tc(VKI) Cycle time ,VP_CLKIN0/1 at 13.3 ns ( 75 MHz) that is the minimum clock requirement to achieve SMPTE 296 mode and make sure you're CPU core voltage should be 1.3V or 1.2V

    Regards

    Antony

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  • 0 in reply to Antony Samsunil
    Intellectual 495 points

     Thanks Antony,

       I  still have few more queries,


    1. The register settings they have provided is only for CnHCFG,CnVCFG0/1 and CnVSIZE,VnHsize only.

         Can you kindly mention if there are any other register settings that needs to be done as well ?

    2. What is the maximum clock frequency that VPCLKin0/1 supports for

        i) BT.656 mode

       ii) BT.1120 mode

      iii) SMTPE 296 mode

      iv) RAW data capture mode ?

    3. Can you kindly specify the register settings for BT.656, BT.1120 , SMTPE 296 , RAW data formats ?

    4. Can you kindly mention as to where the Video port data formed after combining the VPDIN data lines is available in OMAPL13X ?

    5. What do you mean by mentioning " make sure you're CPU core voltage should be 1.3V or 1.2V " ?

          How can I verify the OMAPL138 core  voltage ??

    6. I am trying to interface OV2643 to OMAPL13X. I'm able to read the product id of the device via I2C

    The signals outputted by Vsync and Href lines are in accordance with OMAPL13X VPIF document.

    The PCLK signal (i.e. commonly fed to VP_CLKIN0 and VP_CLKIN1) are at 48Mhz
     , while master clock fed into the image sensor from UI board of EVM development kit  is 24Mhz

    I'm trying to capture raw image data in progressive mode with 1280 * 720p format

    Following are the register configuration used:

    For Channel 0

    Clkedge : Capture data on rising edge

    Datawidth: 8 bits per pixel

    INTLINE: 720p

    FIDINV: 0

    VVINV: 0

    HVINV: 0

    FIELDFRAME: FRAME

    INTRPROG: PROGRESSIVE

    VANC: 0

    HVANC: 0

    INTFRAME: TOP_ONLY

    FID: TOP FIELD

    YCMUX: 0

    CAPMODE: CCD/CMOS RAW capture mode

    CHANEN: 1

    For Channel 1

    Clkedge : Capture data on rising edge

    INTRPROG: PROGRESSIVE

    VANC: 0

    HVANC: 0

    INTFRAME: TOP_ONLY

    FID: TOP FIELD

    YCMUX: 0

    CAPMODE: CCD/CMOS RAW capture mode

    CHANEN: 1

    Interrupt enable

    INTEN: FRAME0 and FRAME1

    Interrupt set register

    INTSET: FRAME0 and FRAME1

    Interrupt Enable Clear

    INTENCLR: FRAME0 and FRAME1

    Emulation Control Register

    EMUCTRL: 0

    DMA size control register

    REQSIZE: 256

    C0TLUMA: 0xC0000000

    C0IMGOFFSET : 1280 * 720 * 2

    The sequence followed is

    - Disable VPIF Interrupts

    - Disable Channel Enable

    - Disable Horizontal and Vertical Ancillary Data

    - Setup the above register values

    - Enable interrupts for FRAME0 and FRAME1

    - Enable clear interrupts for FRAME 0 and FRAME1

    - Enable set interrupts for FRAME 0 and FRAME1

    - Then setup interrupt service routine that gets called for both frame and line interrupt

    Please have a look at the steps taken by me and kindly guide.