Difference between ES1.0 and ES2.0

Hello Vikas,

In a nutshell the changes in the graphics/video modules in OMAP5, between ES1.0 & ES2.0 are the following:

IVA-HD - no change between the two revisions of the device.

Cortex M4 - IPU Subsystem - no change between the revisions of the device.

ISS - the following changes are made in ES2.0:
  - The maximum data rate on the CSI2 interfaces (CSI2_A, CSI2_B and CSI2_C) is increased from 1 Gbps to 1.5 Gpbs per lane.

 - The frequency of RXBYTECLKHS_A, RXBYTECLKHS_B and RXBYTECLKHS_C byte clocks provided by corresponding CSI_PHYs is increased from 125 MHz to 187.5 MHz for OPP_NOM 

OPP_LOW is not supported for VD_CORE in OMAP543x Silicon Revision 2.0

The TCTRL cam_strobe and cam_shutter signals are exported on a second pair of alternative device pads.

CSI3 interface (CAL, MIPI UNIPRO2 and MIPI MPHY) is not supported in OMAP543x Silicon Revision 2.0.

ISP & SIMCOP remain unchanged between the two chip revisions.

DSS Subsystem:

• OPP_LOW removed as not supported at VD_CORE.
• F_CLK increased from 200 to 209.25MHz at OPP_NOM.
• LCDx_CLK increased from 200 to 209.25MHz at 100% OPP_NOM
• DSI1_x_CLK increased from 200 to 209.25MHz at 100% OPP_NOM
• DSS_DISPC_LDCx_PCLK increased from 200 to 209.25MHz at OPP_NOM.
• DSI1_x_TX_BYTECLKHS increased from 125 to 150MHz at OPP_NOM.
• Due to the above the max DSI resulution supported changed to 2048x1536 @ 60 FPS with 24bpp

- DISPC:

  The following new features associated with the DISPC DMA engine are added:
• Microsoft Flip-Immediate feature (on-the-fly Base address update) (GFX, VID1, VID2 and VID3
pipelines). List of registers impacted:
– DISPC_BA0_FLIPIMMEDIATE_EN
– DISPC_IRQENABLE[31] FLIPIMMEDIATEDONE_EN
– DISPC_IRQSTATUS[31] FLIPIMMEDIATEDONE_IRQ
• New support for MFLAG mechanism for dynamic increase of the priority of real time data traffic for the
GFX, VID1, VID2, VID3 and WB pipelines. List of registers impacted:
– DISPC_GLOBAL_MFLAG_ATTRIBUTE
– DISPC_GFX_MFLAG_THRESHOLD
– DISPC_VID1_MFLAG_THRESHOLD

– DISPC_VID2_MFLAG_THRESHOLD
– DISPC_VID3_MFLAG_THRESHOLD
– DISPC_WB_MFLAG_THRESHOLD

• Force 1D access in tiled mode functionality added. List of registers impacted:
– DISPC_GFX_ATTRIBUTES[16] FORCE1DTILEDMODE
– DISPC_VID1_ATTRIBUTES[20] FORCE1DTILEDMODE
– DISPC_VID2_ATTRIBUTES[20] FORCE1DTILEDMODE
– DISPC_VID3_ATTRIBUTES[20] FORCE1DTILEDMODE
– DISPC_WB_ATTRIBUTES[20] FORCE1DTILEDMODE

System performance optimization for 3D rendering via the following formats:
• Line alternative format (ref: HDMI Specification 1.4a)
– Lines from the left and the right frames are interleaved alternatively on the screen to produce a 3D
image.
– Required also to support interleaving column-wise to support all possible screen orientations.
• DISPC_CONFIG1
• DISPC_CONFIG2
• DISPC_CONFIG3
• Frame Packing format (ref: HDMI Specification 1.4a)
– The left and the right frame are sent one after the other.
– To enable multiple 3D displays with 3D GUI overlay, it is required to use a single pipe (graphics or
video) to fetch both left and right frames.
• DISPC_GFX_ATTRIBUTES[10] FRAMEPACKINGMODE
• DISPC_VID1_ATTRIBUTES[8] FRAMEPACKINGMODE
• DISPC_VID2_ATTRIBUTES[8] FRAMEPACKINGMODE
• DISPC_VID3_ATTRIBUTES[8] FRAMEPACKINGMODE
• DISPC_GFX_POSITION2
• DISPC_VID1_POSITION2
• DISPC_VID2_POSITION2
• DISPC_VID3_POSITION2
• DLP 3D TV format
– The left and the right frame are interleaved in a checker board pattern.
– The left and the right frames are sub-sampled by 2 along the diagonal to preserve vertical and
horizontal resolution.
• DISPC_GFX_ATTRIBUTES[20:18] SUBSAMPLINGPATTERN
• DISPC_VID1_ATTRIBUTES2[11:9] SUBSAMPLINGPATTERN
• DISPC_VID2_ATTRIBUTES2[11:9] SUBSAMPLINGPATTERN
• DISPC_VID3_ATTRIBUTES2[11:9] SUBSAMPLINGPATTERN
• BGRA32-8888 format added. List of registers impacted:
– DISPC_GFX_ATTRIBUTES[4:1] FORMAT
– DISPC_VID1_ATTRIBUTES[4:1] FORMAT
– DISPC_VID2_ATTRIBUTES[4:1] FORMAT
– DISPC_VID3_ATTRIBUTES[4:1] FORMAT
– DISPC_WB_ATTRIBUTES[4:1] FORMAT

- MIPI DSI

• Maximum data rate increased from 1000 to 1255.5 Mbps per data pair for four-data lane configuration
• PHY clock incresed from 500 to 627.75MHz at OPP_NOM.

3D Accelerator GPU Subsystem: remains unchanged between the two revisions.

2D Graphics Accelerator: BB2D subsystem is introduced for the first time in OMAP5 ES2.0

For a complete difference between chip revisions please contact your TI representative. There is a delta document available under NDA agreement.

Best Regards,

Yordan