Dear TI E2E community members,
Yet another question on my project towards bounded latency for reading/writing from/to GPIO from the Cortex-M3 subsystem:
Currently I have a piece of software running on the Cortex-M3 subsystem of the OMAP4460 MPSoC which reads and writes from/to the GPIO pins. It seems from the TRM that it is possible to monitor the traffic between the Cortex-M3 subsystem and the bridge between the L3 and L4_PER interconnects. My question is, how to do that from software? I already found an example from the internet, called Omapconf, which does something similar but for traffic between the MPU subsystem (the subsystem with the A9 cores) and the DRAM. I tried to mimic the example and I succeeded to configure the so called statistics collector group registers for my own purpose (SC_LAT1 configuration). However, here comes the challenge: the results of the monitoring are reported to the user through the so called MIPI-STM interface, but I have no idea how to read the results from there from software. Omapconf manages to do so for the purpose of the traffic between the MPU subsystem and the DRAM and hence it should be possible. Please tell me how.
Kind regards,
Richard van Berkel.
