DM814x video DAC power-down

Hi Cory,

Checking the DM814x HDVPSS user's guide, SD_VENC_dacsel is at the same addr (0x48105F50). The difference with DM816x HDVPSS is that in DM814x HDVPSS there are just two DACs, while in DM816x are four. And these two DACs are mapped at bits 25 DAE1 and 24 DAE0. Bits 27 and 26 are in reserved.

Regards,
Pavel

Pavel-

Thanks for the response.  What you describe above (i.e. bits 25 and 24 mapping to DAE1 and DAE0) is pretty much what we'd figured was the case based on a reading of the code.

In actual practice, though, it seems these bits are inactive...?

With DAC0 CVBS output active, I've tried the following:

root@dm814x:~# devmem2 0x48105F50
/dev/mem opened.
Memory mapped at address 0x40212000.
Value at address 0x48105F50 (0x40212f50): 0xE000000

This is expected, DAC0 is active, CVBS output.

root@dm814x:~# devmem2 0x48105F50 w 0x0F000000
/dev/mem opened.
Memory mapped at address 0x40081000.
Value at address 0x48105F50 (0x40081f50): 0xE000000
Written 0xF000000; readback 0xF000000

Per spec, this should enable all DACs; per code this should disable all DACs.  Either way, DAC0 CVBS output is still active.

root@dm814x:~# devmem2 0x48105F50 w 0x00000000
/dev/mem opened.
Memory mapped at address 0x400cb000.
Value at address 0x48105F50 (0x400cbf50): 0xF000000
Written 0x0; readback 0x0

Per spec, this should disable all DACs; per code this should enable all DACs.  Either way, DAC0 CVBS output is still active.

root@dm814x:~# devmem2 0x48105E04
/dev/mem opened.
Memory mapped at address 0x40162000.
Value at address 0x48105E04 (0x40162e04): 0x5

Let's try the VIEN bit in SD_VENC_vmod...

root@dm814x:~# devmem2 0x48105E04 w 0x00000004
/dev/mem opened.
Memory mapped at address 0x40253000.
Value at address 0x48105E04 (0x40253e04): 0x5
Written 0x4; readback 0x4

Deasserting VIEN results in loss-of-signal on both DAC0 and DAC1...

root@dm814x:~# devmem2 0x48105E04 w 0x00000005
/dev/mem opened.
Memory mapped at address 0x4024a000.
Value at address 0x48105E04 (0x4024ae04): 0x4
Written 0x5; readback 0x5

...and re-asserting VIEN results in CVBS output resuming on both DAC0 and DAC1...

Is there something that we're missing here?  I've reviewed the latest DM814x Silicon Errata documentation as well, and see no mention that these bits are invalid and/or the DACs are hardwired "on".  Is there perhaps another way to disable unused DACs (we're interested in this from a radiated EMI perspective).

Thanks!

-Cory

Cory,

Can you try setting/clearing these bits from u-boot and/or from linux kernel. I suspect these bits can not be control from user space (devmem2).

Best regards,
Pavel

Pavel-

I wrote a small driver that simply reads and twiddles the DA1E and DA0E bits each time it's loaded:

#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/types.h>


static void * va_base;


static int __init dm814x_sd_venc_init(void)
{
	void * va;
	u32 sd_venc_dacsel;

	if (!request_mem_region(0x48105E00, 0x200, "dm814x_sd_venc"))
		return -EBUSY;

	if (!(va_base = ioremap_nocache(0x48105E00, 0x200))) {
		release_mem_region(0x48105E00, 0x200);
		return -EBUSY;
	}

	va = (char *)va_base + 0x150;

	sd_venc_dacsel = ioread32(va);
	pr_info(KBUILD_MODNAME ": read      0x%08x\n", sd_venc_dacsel);

	if (sd_venc_dacsel & 0x03000000)
		sd_venc_dacsel &= ~0x03000000;
	else
		sd_venc_dacsel |= 0x03000000;

	iowrite32(sd_venc_dacsel, va);
	pr_info(KBUILD_MODNAME ": write     0x%08x\n", sd_venc_dacsel);

	sd_venc_dacsel = ioread32(va);
	pr_info(KBUILD_MODNAME ": read-back 0x%08x\n", sd_venc_dacsel);

	return 0;
}


static void __exit dm814x_sd_venc_exit(void)
{
	iounmap(va_base);
	release_mem_region(0x48105E00, 0x200);

	pr_info(KBUILD_MODNAME ": Module unload complete.\n");
}


module_init(dm814x_sd_venc_init);
module_exit(dm814x_sd_venc_exit);

MODULE_AUTHOR("Cory T. Tusar <ctusar@videon-central.com>");
MODULE_DESCRIPTION("DM814x SD VENC DAC test driver");
MODULE_LICENSE("GPL");

Loading and unloading this module multiple times via modprobe dm814x_sd_venc && modprobe -r dm814x_sd_venc results in the following output:

dm814x_sd_venc: read      0x0e000000
dm814x_sd_venc: write     0x0c000000
dm814x_sd_venc: read-back 0x0c000000
dm814x_sd_venc: Module unload complete.
dm814x_sd_venc: read      0x0c000000
dm814x_sd_venc: write     0x0f000000
dm814x_sd_venc: read-back 0x0f000000
dm814x_sd_venc: Module unload complete.
dm814x_sd_venc: read      0x0f000000
dm814x_sd_venc: write     0x0c000000
dm814x_sd_venc: read-back 0x0c000000
dm814x_sd_venc: Module unload complete.
dm814x_sd_venc: read      0x0c000000
dm814x_sd_venc: write     0x0f000000
dm814x_sd_venc: read-back 0x0f000000
dm814x_sd_venc: Module unload complete.
dm814x_sd_venc: read      0x0f000000
dm814x_sd_venc: write     0x0c000000
dm814x_sd_venc: read-back 0x0c000000
dm814x_sd_venc: Module unload complete.

DAC status remains unchanged - still always on.

Any other thoughts?

Thanks!

-Cory

Cory,

Cory Tusar said:

DAC status remains unchanged - still always on.

Could you please provide more details about the DAC status? I see that when we set value in the DACXE bits, this value is accepted and can be read afterwards.

Checking the source document for this DM814x HDVPSS user guide, I see we have 4 bits for the SD VENC DAC, same as DM816x HDVPSS user guide, bits 27,26,25 and 24. I experiment with this register and [27:24] bit field. By default in u-boot, the value is 0x00000000. I can successfully set all for bits to 0x1, I write 0x010000000, 0x03000000, 0x07000000 and 0x0F000000. But when I try with 0x1F000000, I read back 0x0F000000. Which means we have something mapped on the [27:24] bits, same as DM816x HDVPSS.

When I set 0x0 (disable) in some of the 27:24 bits, the value is accepted, meaning the corresponding DAC is powered down. Why you think the DAC is not powered down? Do I miss something?

Regards,
Pavel

Cory,

Some info in the below e2e thread;

http://e2e.ti.com/support/arm/sitara_arm/f/791/p/212910/757932.aspx#757932

Regards,
Pavel

Pavel Botev said:

Could you please provide more details about the DAC status? I see that when we set value in the DACXE bits, this value is accepted and can be read afterwards.

Yes, the values of the DACXE bits seem to be set and read-back just fine.

Pavel Botev said:

Checking the source document for this DM814x HDVPSS user guide, I see we have 4 bits for the SD VENC DAC, same as DM816x HDVPSS user guide, bits 27,26,25 and 24. I experiment with this register and [27:24] bit field. By default in u-boot, the value is 0x00000000. I can successfully set all for bits to 0x1, I write 0x010000000, 0x03000000, 0x07000000 and 0x0F000000. But when I try with 0x1F000000, I read back 0x0F000000. Which means we have something mapped on the [27:24] bits, same as DM816x HDVPSS.

Agreed, the above matches with our experience (i.e. we can write and read-back bits [27:24] but not other reserved bits).

Pavel Botev said:

When I set 0x0 (disable) in some of the 27:24 bits, the value is accepted, meaning the corresponding DAC is powered down. Why you think the DAC is not powered down? Do I miss something?

Regardless of the value of DAC0E, DAC0 is always "on"; an active video signal is present when the DM814x DAC output is probed with a 'scope.  The same is true for DAC1E.

Also, if I clear VIEN to '0' in SD_VENC_vmod, both DACs show no active video signal on the 'scope (which is interesting, but doesn't help us mitigate radiated EMI from the unused DAC1)

I haven't dug our DM814x EVM out of storage to verify, but I suspect I'd find the same behavior on that platform as well given that our board's SD video output looks very similar to the EVM.

-Cory

Cory,

Cory Tusar said:

I haven't dug our DM814x EVM out of storage to verify, but I suspect I'd find the same behavior on that platform as well given that our board's SD video output looks very similar to the EVM.

Could you check this on the DM814x EVM. I can not find any other steps required to power down these DACs, only the 27:24 bits.

Regards,
Pavel

Cory,

Can you also check the behaviour of the SD DACs when setting bit SD_DAC_CTRL[2] OFFMODE to 0x1. If there is a problem to write it , make sure unlocked protected system control MMR regions (0x600 – 0x800) – by writing  0xF757_FDC0 to MMR_LOCK1 registers (base_addr= 0x4814_0000  offset = 64h, reset=0xFDF45530)

Regards,
Pavel

Pavel-

Pavel Botev said:

Could you check this on the DM814x EVM. I can not find any other steps required to power down these DACs, only the 27:24 bits.

We've finally had a chance to reproduce this on our DM814x EVM using EZSDK-5.05.02.00.  Steps are as follows:

1. Connect CVBS output from EVM J9 to monitor.
2. Boot EZSDK from SD card.
3. Login as 'root'.
4. Enable color-bar output.
   
   devmem2 0x48105E04 w 0x00000015
5. "Enable" all SD_VENC DACs as CVBS outputs.
   
   devmem2 0x48105F50 w 0x0F000000
6. "Disable" all SD_VENC DACs.
   devmem2 0x48105F50 w 0x00000000
7. Note CVBS video output is still active.

At this point it appears - based on empirical evidence - that these bits are ignored, and the DACs are simply hard-wired "ON" in the DM814x.  Can you confirm?

Best regards,
-Cory

Cory,

Can you try also with the below register/bits:

Set bit SD_DAC_CTRL[2] OFFMODE to 0x1

Clear bit SD_DAC_CTRL[3] PBNBGz to 0x0

Clear bit SD_DAC_CTRL[4] PBNDACz to 0x0

The SD_DAC_CTRL register is part of the Control Module register map (offset 0x670). You can find this register in the DM814x TRM, chapter 3 Control Module.

Best regards,
Pavel