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66AK2H12 smartreflex

Scott Greeley1
Intellectual 585 points
Other Parts Discussed in Thread: 66AK2H12

The latest data manual for 66AK2H12 (rev E) says that the default Smartreflex (AVS) interface is '4pin 6-bit dual phase VCNTL', and shows timing diagram for this on pg 274 and 275.   Is the '4pin 6-bit dual phase VCNTL' the only supported interface?   If not, where are the timing diagrams for the other interfaces?

How often does CVDD voltage command occur, and when does it first occur relative to the power sequence events (Figure 10-1)?    

Is Table 1 of the Keystone I Hardware Design Guide (sprabi2c) valid for 66AK2H12?  If not, what is the translation from VID bits to CVDD voltage command?  

For the 66AK2H12, are the VCNTL pins open drain, and do they need pull-up resistors?   If so, what value is recommended for the pull-up and to what voltage rail?

When will the Keystone II Hardware Design Guide be released?

thanks.

  • 0
    TI__Mastermind 46460 points

    Scott,

    We also support a 6-pin/6-bit interface. There is no critical timing for this interface mode.

    The AVS voltage change commands may occur randomly as needed for temperature driven performance variation occurs.

    The time delay from reset release to AVS voltage change command is not characterized.  We only indicate it will occur soon thereafter.

    The VID code table in the KeyStone I Hardware Design Guide is equally valid for KS II.

    The VCNTL pins are open drain.  They require pull-up resistors to DVDD18.  A resistor value of 10K is reasonable.

    The new KS I and KS II Hardware Design Guide releases are targetted for the end of January.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Intellectual 585 points

    Tom,

    Section 10.2.4 of revE data manual refers to VCNTL[3:0] signals for the 4-pin 6-bit VID interface.   However, Tables 8-29 and 8-31 refer to using VCNTL[5:2].    Also, the K2H_K2EVM eval board schematic only connects VCNTL[5:2].

    Assuming the eval board is correct, would you provide correction for section 10.2.4, so we know which pins to monitor for the 4-pin 6-bit VID interface?

    thanks.

    Scott

  • 0 in reply to Scott Greeley1
    TI__Mastermind 42545 points

    Hi Scott,

    Section 10.2.4 of the data manual is incorrect. When connecting the 66AK2H12 in 4-pin 6-bit dual-phase mode, VCNTL[5:2] should be used as specified in Table 8-29. The figure below illustrates the connection between the 66AK2H12 and a UCD92xx power supply controller, including the level translation logic.

    Regards, Bill