Problem with PCIe transmission between C6678 and Virtex-6

Alexander Z

We are using pcie_init example from http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/155435.aspx and Endpoint for PCI Express and PCI Express Endpoint Core sample application design on Virtex-6 FPGA. The DSP works as RC and the FPGA as EP. We changed location of .dstBufSec section (DDR3->L2SRAM). My goal is to trasmit 0xdeadbeef and recieve it back. The output on the console of CCS is:

**********************************************
* PCIe Test Start *
* RC mode *
**********************************************

Version #: 0x01000003; string PCIE LLD Revision: 01.00.00.03:Nov 19 2012:16:03:31

Power domain is already enabled. You probably re-ran without device reset (which is OK)
PCIe Power Up.
PLL locked.
PLL configured.
Successfully configured Inbound Translation!
Location: 0 PMEnable: 0x0
Location: 0 pmeStatus: 0x0 pmeReqID: 0x0
Location: 0 aspmL1: 0x0 l1entry: 0x3 l0sentry: 0x3 commnf: 0xf numfts: 0x64 ackfreq: 0x0
Starting link training...
Link is up.
Location: 1 PMEnable: 0x0
Location: 1 pmeStatus: 0x1 pmeReqID: 0x0
Location: 1 aspmL1: 0x0 l1entry: 0x0 l0sentry: 0x0 commnf: 0x0 numfts: 0x0 ackfreq: 0x0
CFG SETUP before enumeration: bus 0, device 0, func 0, type 0
i 0, VID 6012, DEV 10ee
offset: 0x0 : 601210ee 00100000 05000000 00000000
offset: 0x10 : 70000000 00000000 00000000 00000000
offset: 0x20 : 00000000 00000000 00000000 000710ee
offset: 0x30 : 00000000 00000040 00000000 000001ff
offset: 0x40 : 78034801 00000008 00806005 00000000
offset: 0x50 : 00000000 00000000 00000000 00000000
offset: 0x60 : 02029c10 00008e00 00002810 0003f421
offset: 0x70 : 00110000 00000000 00000000 00000000
offset: 0x80 : 00000000 00000002 00000000 00000000
offset: 0x90 : 00010000 00000000 00000000 00000011
offset: 0xa0 : 00000000 00000000 00000000 00000000
offset: 0xb0 : 00000000 00000000 00000000 00000000
offset: 0xc0 : 00000000 00000000 00000000 00000000
offset: 0xd0 : 00000000 00000000 00000000 00000000
offset: 0xe0 : 00000000 00000000 00000000 00000000
offset: 0xf0 : 00000000 00000000 00000000 00000000
offset: 0x100 : 10c10003 01000a35 00000001 00000000
offset: 0x110 : 00000000 00000000 00000000 00000000
offset: 0x120 : 00000000 00000000 0001000b 01811234
offset: 0x130 : 00000000 00000000 00000000 00000000
offset: 0x140 : 00000000 00000000 00000000 00000000
offset: 0x150 : 00000000 00000000 00000000 00000000
offset: 0x160 : 00000000 00000000 00000000 00000000
offset: 0x170 : 00000000 00000000 00000000 00000000
offset: 0x180 : 00000000 00000000 00000000 00000000
offset: 0x190 : 00000000 00000000 00000000 00000000
offset: 0x1a0 : 00000000 00000000 00000000 00000000
offset: 0x1b0 : 00000000 00000000 00000000 00000000
offset: 0x1c0 : 00000000 00000000 00000000 00000000
EP: bar#0, base 0x07000000, prefetch 0x0, type 0x0, memSpace 0x0
Local - bar#1, base 0x09000000, prefetch 0x0, type 0x0, memSpace 0x0
Location: 0 BusEnable: 0x1 Memory bit is: 0x1
Location: 1 BusEnable: 0x1 Memory bit is: 0x1
Done enumeration OK
LnkBWStat: 0x0, dllactive: 0x1, sltClk: 0x1, LnkTrn: 0x0, commonClk: 0x0, activeLnkPM: 0x0
base: 00000000 ec200000 00000000 ec200000
read: 00000000 71e2199f bebebebe bebebebe
Location: 0 PMEnable: 0x0
Location: 0 pmeStatus: 0x0 pmeReqID: 0x0
Location: 0 aspmL1: 0x0 l1entry: 0x3 l0sentry: 0x3 commnf: 0xf numfts: 0x64 ackfreq: 0x0

It shows that link is up, the word 0xdeadbeef was transmitted, and I recieve 0x00000000 back. What is wrong? Why I can't recieve back 0xdeadbeef?

over 11 years ago

0 Steven Ji over 11 years ago

TI__Genius 12065 points

Did you enable the Outbound translation in RC (DSP) please? If so, what is the Outbound translation setup please?

It looks like you setup EP BAR0 to be 0x70000000, so you need to make sure the PCIe packets from RC is translated to 0x70000000 range after the OB translation in RC. Otherwise EP will not receive the packets correctly and the data transfer will fail.

It will be good to share your source code as well, then we could take a look and understand how the transaction and translation is configured.

0 Alexander Z over 11 years ago in reply to Steven Ji

Prodigy 30 points

Thank you for your reply. In my code the outbound translation is set as Pcie_cfgObOffset(handle, obAddrLo, obAddrHi, region) and obAddrLo = 0x90000000. Configure address translation is

/* Configure Address Translation */
    
    barCfg.location = pcie_LOCATION_LOCAL;
    barCfg.mode     = pcie_RC_MODE;
    barCfg.base     = PCIE_IB_LO_ADDR_M;
    barCfg.prefetch = pcie_BAR_NON_PREF;
    barCfg.type     = pcie_BAR_TYPE32;
    barCfg.memSpace = pcie_BAR_MEM_MEM;
    barCfg.idx      = PCIE_BAR_IDX_M;

and

/* Configure Address Translation */
barCfg.location = pcie_LOCATION_REMOTE;
barCfg.mode     = pcie_EP_MODE;
barCfg.base     = 0x60000000;
barCfg.prefetch = pcie_BAR_NON_PREF;
barCfg.type     = pcie_BAR_TYPE32;
barCfg.memSpace = pcie_BAR_MEM_MEM;
barCfg.idx      = 0;

Here is my source code

8400.pcie_init.zip

0 Steven Ji over 11 years ago in reply to Alexander Z

TI__Genius 12065 points

Alexander,

I think there is issue with your obAddrLo setup. If you set BAR0 in EP to be 0x70000000, you should set your OB_Addr in RC to be 0x70000000 as well. And there is one symbol defined in the header file that you could use:

#define PCIE_OB_LO_ADDR_M 0x70000000

So is there any reason to use 0x90000000 instead of 0x70000000 in your OB translation setup below please?

if ((retVal = pcieObTransCfg (handle, 0x90000000/*PCIE_OB_LO_ADDR_M*/, 0 /*PCIE_OB_HI_ADDR_M*/, 0 /*PCIE_OB_REGION_M*/)) != pcie_RET_OK)
{
System_printf ("Failed to configure Outbound Address Translation (%d)\n", (int)retVal);
exit(1);
}

Please change it to 0x70000000 and give a try with your testing again to see if the transactions could be completed correctly.

0 Alexander Z over 11 years ago in reply to Steven Ji

Prodigy 30 points

Thank you for your help. It was very useful to solve my problem. I don't understand about the adress translation fully. Now I recieved back the word 0xdeadbeef.

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Problem with PCIe transmission between C6678 and Virtex-6