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C6657 SmartReflex Timing

David F
Intellectual 645 points
Other Parts Discussed in Thread: UCD9222

As our C6657 core supply design was based on the latest available hardware documentation back in 2012 (ie. Figs 17&18 of SPRABI2B, March 2012), the UCD side of the VID signals are not pulled to 3.3V.

1. Is the lockout mechanism on the UCD9222 a valid approach to dealing with misbehaving VID inputs early in the power cycle?

2. If so, TI documentation is not clear on the timing relationship between valid power rails (specifically CVDD and I/O supplies), reset, and the C6657 driving its VID outputs. Specifically what is the timing relationship?

  • 0
    TI__Mastermind 42545 points

    Hi David,

    We can't specify the timing relationship between the release of the reset and the VID update. It's dependent on the bootmode and boot devices used in your system. Using the lockout mechanism of the UCD9222 is a possible solution but you will have to determine the timing from when the UCD9222 begins it's delay to the time that the VID is issued in your system. You'll have to contact the power supply team to determine when the UCD9222 delay begin. I'm not sure if it's based off of the enable of the controller or if it begins to count as soon as the power is applied to the UCD9222. 

    We solved this problem by disabling the drivers of the level translator until the DVDD18 power supply is valid as specified in rev C of the Hardware Design Guide. This will prevent the rising VCNTL signals from causing false transitions on the 3.3V side of the translator.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 645 points

    Thanks, Bill.

    Assuming we boot off PCIe, can you narrow it down for us at all, if only in terms of where in the boot sequence?

    We would feel pretty safe aiming for a delay time somewhere in between the I/O supply being valid and reset being deasserted, but knowing what the outer margin is might be helpful.

    Dave

  • 0 in reply to David F
    TI__Mastermind 42545 points

    Hi Dave,

    I'm sorry I don't have that information. When we implemented that approach on one of our early EVMs, we measured the delay from the IO voltage to when the command was issued after reset using an oscilloscope.  We used that information to program the delay. We found that the same boot mode gave us consistent operation.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 645 points

    Bill, can you at least confirm that the VID will not be sent by the C6657 until after we have taken it out of reset (POR + RESET + RESETFULL) ?

    This would allow us to delay taking the part out of reset until after the lockout has expired...

    Dave

  • 0 in reply to David F
    TI__Mastermind 42545 points

    Hi Dave,

    The VID value will be transmitted after the reset(PORz+RESET+RESETFULL) has been released. The delay from the rising edge of RESETFULL to the VID value will vary based on boot mode. In addition the time from when the CDC92xx begins counting the delay to the point where the power supplies are active and the RESETFULL goes high is dependent on your design. 

    Regards, Bill