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Information on I-Cache & D-Cache in u-boot

Ramesh071
Intellectual 620 points

Hi,


I'm working on omap5 based evm.

I'm having latest u-boot source code. For my evm I want enable the I-Cache and D-Cache in u-boot to speed up the boot process.

I know in u-boot configuration file I can enable by making on.

But If I enable it,  what is impact on my system. After enabling I can directly run kernel or what.

Kindly Give some more information on this.

Thanks in advance for your info.

Thanks

Ramappa

  • 0
    TI__Guru**** 161600 points

    Hello,

    Yes you should be able to directly run the kernel after enabling ICache & DCache in u-boot. 

    As you stated this will optimize your u-boot & reduce boot time of your system.

    For L1I (ICache) & L1D (DCache) programming considerations you should consult ARM Cortex A15 MPCore Technical reference manual, available at http://infocenter.arm.com/help/index.jsp.

    You should ensure that cache coherence is taken care of. 

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Intellectual 620 points

    Hi Yordan,

    I have enabled the I-Cache & D-Cache with DMA in u-boot

    To achieve cache coherency,  before starting DMA I'm invalidating the cache as follows.

    here 'buf' is DMA buffer.

    start = buf;
    end = start + (blkSiz * numBlk);

     /* Invalidating the DMA Buffer in D-Cache */
     invalidate_dcache_range(start, end);


    But I'm getting the following ERROR.

    ERROR: v7_dcache_inval_range - start address is not aligned - 0xdeefb310                                              
    ERROR: v7_dcache_inval_range - stop address is not aligned - 0xdeeff710

     

    Kindly help me to resolve this issue.

     

     

    Thanks

    Ramappa

     

     

  • 0 in reply to Ramesh071
    TI__Intellectual 1340 points

    Isn't this the same issue you posted in another thread [1]?

     

    --

    [1] http://e2e.ti.com/support/omap/f/885/p/315307/1101178.aspx

  • 0 in reply to Ramesh071
    TI__Guru**** 161600 points

    Hello Ramappa,

    Looking the GLSDK 6_03 u-boot sources I found the following guidance about using caches in u-boot:
    "- A suitable buffer can be alloced on the stack using the
      ALLOC_CACHE_ALIGN_BUFFER macro."
    Have you tried allocating a buffer using the ALLOC_CACHE_ALIGN_BUFFER macro? The complete document is called README.arm-caches and is located in u-boot/doc folder. The mentioned macro & its description can be found at u-boot/include/common.h

    Best Regards,

    Yordan