Configuring cache and EDMA3 on C674x platforms, confused about documentation

A month to the day you posted your question. We usually do better than that if the question is something we can answer.

Martin Alnaes said:

I have two evaluation cards, one OMAP L137 from Spectral Digital and one OMAP L138 from Logic. I'm only using the DSPs, not the ARM.

The L137 and L138 have a lot of technical differences. I am not going to list them to you, but will say to look at the two datasheets to see how large the L1 and L2 memories are and to see what important differences there might be.

Martin Alnaes said:

The EDMA3 documentation for C674x refers to csl_cache.h and functions like CACHE_wb, which I haven't found anywhere.

My understanding is that there is no separate CSL for 674x, and I see that csl.h is part of the PSP, but I find no csl_cache.h in PSP 1.30.

CSL functions start with CSL_ and a module name. CACHE_wb is a DSP/BIOS command. The header file bcache.h is in the BIOS include folder.

I thought we were at least supplying register-level CSL for the DSP-only parts.

Martin Alnaes said:

However, including <bcache.h> and using BCACHE_wb etc. seems to work on my 6748 card, giving faster execution with cache turned on than off. Running the same code on the 6747 yields no change in speed from turning the cache on and off. Is there any difference between these platform w.r.t. cache?

BCACHE_wb is a coherency command that is needed when handling issues with EDMA moving data into and out of memory that is also accessed by the DSP. It totally depends on what you are doing in the program as to whether or not coherency commands are needed. And they will normally have no effect on the improved program access performance, which will be great with cache on. On the data said, they will not have any positive effect on performance, either, but can have a huge effect on correct operation by avoiding the coherency problems. The cache memory user's guide has good explanations about coherency and coherency commands.

Martin Alnaes said:

The documentation for DSP/BIOS 5.4 marks bcache as C64+ only. To which extent does the EDMA3 documentation for C64+ apply to C674x?

The C674x core is a superset of the C64x+ core, and the architecture of the EDMA3 module in these chips is the same as any other chip that has EDMA3 in it. But each EDMA3 implementation can be a little different. Again, refer to the datasheet to find out specifics about the different implementations. And make sure you are using libraries that are specifically for the C674x - if they are built for the C64x+, the instructions are all compatible but addresses and other settings might be different. And make sure you select the right device and core in the DSP/BIOS setup so all the settings will be right.

Martin Alnaes said:

bios.GBL.C64PLUSMAR0to31    = 0xFF;
bios.GBL.C64PLUSMAR32to63   = 0xFF;

If DSP/BIOS uses C64PLUSxxxx in the labels for C674x cores, I am a little sad. The architecture is so close that it would make sense to save time an leave them the same when moving to the new core, but I wish they would change it. Or is it possible that you have not set the core ID correctly and the GUI would have used different labels? Sounds like you do not like using the GUI in CCS for your settings.

The parameters you are setting above are for 32 MAR bits, each. You need to use 0xFFFFFFFF to set all of them.