PRU memory/peripheral access protection with MMU

Tobias Matschke

Hello!

I am currently researching, if a PRU's accesses to the global address domain are run through the MMU. The goal is to protect given memory areas and/or peripherals from being accessed by PRU code.

Thanks in advance!

Greetings

Tobias

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Hi Tobias,

The PRU-ICSS is not supported by TI but community support may be offered at http://www.beagleboard.org/Community/Forums. Some resources, including a reference manual can be found at https://github.com/beagleboard/am335x_pru_package.

0 Frank Walzer over 11 years ago

TI__Mastermind 44306 points

Tobias,

you might want to rephrase the question to work around the PRU issue :-). There are other bus masters in the device...

Anyway as the MMU is part of the ARM core block it is not visible at all to the other bus masters. So virtual addresses are not available for them I think. Otherwise all bus traffic would have to be routed through the ARM MMU. Not a good idea for system performance where we make heavy use of parallel bus transfers. In addition I don't know how that should work logically as MMU context typically changes with task context in HLOS. But how should the PRU know about that?

Regards.

Processors

Processors forum

PRU memory/peripheral access protection with MMU