Hi
I'm attaching the the C file done by me after going through several posts on this forum regarding VPIF raw data capture.
Can any body kindly check the code and guide me in storing and viewing the captured image in DDR2 data section i.e. 0xc0000000 to 0xcfffffff .
Displaying the captured image in memory browser window of Code composer studio.
I'm using board support libraries of logic pd and staterware of OMAPL138
All raw_h_valid and raw_v_valid signals are appearing in Sync with the timing diagram provided by VPIF of Omapl138 an d clock on CLK_VIN0/1 is 75Mhz. I'm getting the interrupts according to TRM of OMAPl138 with line interrupt for every 720 lines.
I'm trying to capture raw image in 720p format .
I'm trying to store the data in DDR2 section i.e. 0xc0000000 to 0xcfffffff .
If i check through the memory browser then it shows nothing, but if i try printing the data from section used then it keeps on repeating 4 32 bit words repetitively irrespective the length printed.
//-----------------------------------------------------------------------------
// \file main.c
// \brief implementation of main() to test bsl drivers.
//
//-----------------------------------------------------------------------------
#include "stdio.h"
#include "types.h"
#include "evmomapl138.h"
#include "evmomapl138_timer.h"
#include "evmomapl138_gpio.h"
#include "evmomapl138_i2c.h"
#include "omapl138_OV2643.h"
#include "evmomapl138_mmcsd.h"
#include "OV2643_reg_setup.h"
//-----------------------------------------------------------------------------
// Private Defines and Macros
//-----------------------------------------------------------------------------
// uncomment this define if running without gel initialization.
// #define NO_GEL (1)
#define Horizontal_pixel_cnt 1280
#define Vertical_pixel_cnt 720
#define Video_Buf Horizontal_pixel_cnt*Vertical_pixel_cnt
#ifdef _TMS320C6X
#include "dspcache.h"
#else
#include "cp15.h"
#ifdef gcc
#define restrict
#endif
#endif
//-----------------------------------------------------------------------------
// Static Variable Declarations
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Private Function Prototypes
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Public Function Definitions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// \brief entry point for bsl test code.
//
// \param none.
//
// \return none.
//-----------------------------------------------------------------------------
int main(void)
{
unsigned int results = 0;
unsigned int rtn;
// PREVIEW_PARAM _param;
#if NO_GEL
EVMOMAPL138_init();
EVMOMAPL138_initRAM();
#endif
// init the us timer and i2c for all to use.
USTIMER_init();
I2C_init(I2C0,I2C_CLK_400K);
rtn = OV2643_init();
OV2643_soft_reset();
if (rtn != ERR_NO_ERROR)
{
printf("error initializing OV2643!\r\n");
return (rtn);
}
#ifndef _TMS320C6X
unsigned int index;
#endif
/* Setting the Master priority for the VPIF and LCD DMA controllers to highest level*/
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI1) &= 0x00FFFFFF;
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_MSTPRI2) &= 0x0FFFFFFF;
#ifdef _TMS320C6X
/*Set MAR bits and configure L1 cache*/
CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x10000000);
CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K );
printf("Cache enabled \r\n");
#else
/*Sets up 'Level 1" page table entries.
* The page table entry consists of the base address of the page
* and the attributes for the page. The following operation is to
* setup one-to-one mapping page table for DDR memory range and set
* the attributes for the same. The DDR memory range is from 0xC0000000
* to 0xCFFFFFFF. Thus the base of the page table ranges from 0xC00 to
* 0xCFF. Cache(C bit) and Write Buffer(B bit) are enabled only for
* those page table entries which maps to DDR RAM and internal RAM.
* All the pages in the DDR range are provided with R/W permissions*/
for(index = 0; index < (4*1024); index++)
{
if((index >= 0xC00 && index < 0xD00)|| (index == 0x800))
{
pageTable[index] = (index << 20) | 0x00000C1E;
}
else
{
pageTable[index] = (index << 20) | 0x00000C12;
}
}
/*Configures translation table base register
* with pagetable base address.*/
CP15TtbSet((unsigned int )pageTable);
/*Enables MMU*/
CP15MMUEnable();
/* Enable Instruction Cache*/
CP15ICacheEnable();
/*Enable Data Cache*/
CP15DCacheEnable();
#endif
ov2643_cam_table_write(OV2643_REGS_720p);
VPIF_raw_capture_init();
if (rtn != ERR_NO_ERROR)
{
printf("error initializing OV2643!\r\n");
return (rtn);
}
// TEST IMAGE_SENSOR
//------------------
while(1);
if (results != ERR_NO_ERROR)
printf("\r\n\r\n********** OMAP-L138 TEST FAILED **********\r\n\r\n");
else
printf("\r\n\r\n********** OMAP-L138 TEST PASSED **********\r\n\r\n");
}
#include "omapl138_OV2643.h"
#define HW_PSC_VPIF 9
//-----------------------------------------------------------------------------
// Private Defines and Macros
//-----------------------------------------------------------------------------
// i2c defines.
//-----------------------------------------------------------------------------
// Private Function Prototypes
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Public Function Definitions
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// .
//-----------------------------------------------------------------------------
volatile unsigned int captured=0, changed=0, updated=3, processed=1;
/* page tables start must be aligned in 16K boundary */
#ifdef __TMS470__
#pragma DATA_ALIGN(pageTable, 16384);
static volatile unsigned int pageTable[4*1024];
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=16384
static volatile unsigned int pageTable[4*1024];
#elif _TMS320C6X
#else
static volatile unsigned int pageTable[4*1024] __attribute__((aligned(16*1024)));
#endif
//static uint16_t slave_i2c_addr = 0;
unsigned short picBuf1[VBUF_SIZE*2];
#pragma DATA_SECTION(picBuf1,"PICTURE");
unsigned short picBuf2[VBUF_SIZE*2];
#pragma DATA_SECTION(picBuf2,"PICTURE");
unsigned short picBuf3[VBUF_SIZE*2];
#pragma DATA_SECTION(picBuf3,"PICTURE");
unsigned short *picBuffer[3];
unsigned int frame=0;
unsigned int getPIC=0;
unsigned int curPicBuff;
unsigned int prevfram;
void VPIFIsr(void)
{
unsigned int status;
uint16_t i,curr;
#ifdef _TMS320C6X
IntEventClear(SYS_INT_VPIF_INT);
#else
IntSystemStatusClear(SYS_INT_VPIF);
#endif
status = VPIFInterruptStatus(SOC_VPIF_0_REGS, VPIF_ERROR_INT | VPIF_FRAMEINT_CH1 | VPIF_FRAMEINT_CH0);
/* Initialize buffer addresses for a new frame */
if (getPIC&&(VPIF_FRAMEINT_CH0 & status)){
curr = getCurPIC();
/*printf("Current read frame %d\r\n",curr);
for(i=0;i < 100; i++)
printf("%d 0x%x,\r\n",i,picBuf1[curPicBuff + i]);*/
frame++;
curPicBuff=frame%3; //marks the current captured frame
printf("Current read frame %d\r\n",curPicBuff);
if (frame==99999) frame=0;
switch(curPicBuff)
{
case 0:
printf("1\r\n");
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_LUMA, (unsigned int) picBuf1, VBUF_SIZE*2);
VPIFInterruptDisable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 |VPIF_FRAMEINT_CH1 | VPIF_FRAMEINT_CH2 | VPIF_FRAMEINT_CH3 | VPIF_ERROR_INT);
USTIMER_delay(2 * DELAY_HALF_SEC);
if(picBuf1[0]!= NULL)printf("DATA1\r\n");
getPIC=0;
break;
case 1:
printf("2\r\n");VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_LUMA, (unsigned int) picBuf2, VBUF_SIZE*2);
VPIFInterruptDisable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 |VPIF_FRAMEINT_CH1 | VPIF_FRAMEINT_CH2 | VPIF_FRAMEINT_CH3 | VPIF_ERROR_INT);
USTIMER_delay(2 * DELAY_HALF_SEC);
if(picBuf2[0]!= NULL)printf("DATA2\r\n");
getPIC=0;
break;
case 2:
printf("3\r\n");
VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD,
VPIF_LUMA, (unsigned int) picBuf3, VBUF_SIZE*2);
VPIFInterruptDisable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 |VPIF_FRAMEINT_CH1 | VPIF_FRAMEINT_CH2 | VPIF_FRAMEINT_CH3 | VPIF_ERROR_INT);
USTIMER_delay(2 * DELAY_HALF_SEC);
if(curPicBuff == 2)
VPIFInterruptDisable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 |VPIF_FRAMEINT_CH1 | VPIF_FRAMEINT_CH2 | VPIF_FRAMEINT_CH3 | VPIF_ERROR_INT);
if(*picBuf3!= NULL){printf("DATA3\r\n");
for(i=0 ; i < 1843200; i++)
printf("%d %d\r\n",i,picBuf3[0+i]);}
getPIC=0;
break;
default:
printf("Improper frame\r\n");
}
if(curPicBuff != 2)
VPIFInterruptEnable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 );
}
/* clear interrupt */
VPIFInterruptStatusClear(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
// if error interrupt occurs, report error
if ((status & VPIF_ERROR_INT)) {
printf(" Channel 0 & 1 error");
}
swapBuff();
}
/*
** Configures arm/dsp interrupt controller to generate frame interrupt
*/
void SetupIntc(void)
{
/* Setup DSP or ARM interrupt controller */
#ifdef _TMS320C6X
/* Initialize the DSP interrupt controller */
IntDSPINTCInit();
/* Register ISR to vector table */
IntRegister_DSP(C674X_MASK_INT5, VPIFIsr);
/* Map system interrupt to DSP maskable interrupt */
IntEventMap(C674X_MASK_INT5, SYS_INT_VPIF_INT);
/* Enable DSP maskable interrupt */
IntEnable_DSP(C674X_MASK_INT5);
/* Register LCD ISR to vector table */
IntRegister_DSP(C674X_MASK_INT6, LCDIsr);
/* Map system interrupt to DSP maskable interrupt for LCD */
IntEventMap(C674X_MASK_INT6, SYS_INT_LCDC_INT);
/* Enable DSP maskable interrupt for LCD */
IntEnable_DSP(C674X_MASK_INT6);
/* Enable DSP interrupts */
IntGlobalEnable_DSP();
#else
/* Initialize the ARM Interrupt Controller.
IntAINTCInit();
Register the ISR in the Interrupt Vector Table.
IntRegister(SYS_INT_VPIF, VPIFIsr);
Set the channel number 2 of AINTC for LCD system interrupt.
IntChannelSet(SYS_INT_VPIF, 2);
Enable the System Interrupts for AINTC.
IntSystemEnable(SYS_INT_VPIF);
Enable IRQ in CPSR.
IntMasterIRQEnable();
Enable the interrupts in GER of AINTC.
IntGlobalEnable();
Enable the interrupts in HIER of AINTC.
IntIRQEnable();*/
#endif
printf("Set up interrupt controller \r\n");
}
void swapBuff(){
getPIC=1;
}
unsigned int getCurPIC(){
return curPicBuff;
}
unsigned int prevframe(){
if(curPicBuff > 0)
{
prevfram = --curPicBuff;
}
return prevfram;
}
void VPIF_raw_capture_init()
{
picBuffer[0] = picBuf1;
picBuffer[1] = picBuf2;
picBuffer[2] = picBuf3;
SetupIntc();
printf("VPIF Init \r\n");
/* Power on VPIF */
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_VPIF, PSC_POWERDOMAIN_ALWAYS_ON,PSC_MDCTL_NEXT_ENABLE);
/* Setup VPIF pinmux */
configReceivePinMux();
//SetUpVPIFRx();
// Disable interrupts
VPIFInterruptDisable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 |VPIF_FRAMEINT_CH1 | VPIF_FRAMEINT_CH2 | VPIF_FRAMEINT_CH3 | VPIF_ERROR_INT);
VPIFCaptureHancDisable(SOC_VPIF_0_REGS,VPIF_CHANNEL_0);
VPIFCaptureHancDisable(SOC_VPIF_0_REGS,VPIF_CHANNEL_1);
VPIFCaptureVancDisable(SOC_VPIF_0_REGS,VPIF_CHANNEL_0);
VPIFCaptureVancDisable(SOC_VPIF_0_REGS,VPIF_CHANNEL_1);
// Disable capture ports
VPIFCaptureChanenDisable(SOC_VPIF_0_REGS, VPIF_CHANNEL_1);
VPIFCaptureChanenDisable(SOC_VPIF_0_REGS, VPIF_CHANNEL_0);
// CH0, CH1 frame interrupt: Top field V-sync only
VPIFCaptureIntframeConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_FRAME_INTERRUPT_TOP);
//VPIFCaptureIntframeConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_1, VPIF_FRAME_INTERRUPT_TOP_BOTTOM);
VPIFCaptureRawIntlineConfig(SOC_VPIF_0_REGS,720);
/*VPIFCaptureClkedgeModeSelect(SOC_VPIF_0_REGS,VPIF_CHANNEL_0,VPIF_CLKEDGE_RISING);
VPIFCaptureClkedgeModeSelect(SOC_VPIF_0_REGS,VPIF_CHANNEL_1,VPIF_CLKEDGE_RISING);*/
// RAW mode
VPIFCaptureCapmodeModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_CAPTURE_RAW);
VPIFCaptureCapmodeModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_1, VPIF_CAPTURE_RAW);
VPIFCaptureModeConfig(SOC_VPIF_0_REGS, VPIF_CAPTURE_RAW, VPIF_CHANNEL_0, 0, (VPIFVbufParam*) 0);
VPIFCaptureModeConfig(SOC_VPIF_0_REGS, VPIF_CAPTURE_RAW, VPIF_CHANNEL_1, 0, (VPIFVbufParam*) 0);
// 8 bit data
VPIFCaptureRawDatawidthConfig(SOC_VPIF_0_REGS, VPIF_RAW_EIGHT_BPS);
// Progressive capture
VPIFCaptureIntrprogModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_CAPTURE_PROGRESSIVE);
VPIFCaptureIntrprogModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_1, VPIF_CAPTURE_PROGRESSIVE);
// Size of the REQSIZE
VPIFDMARequestSizeConfig(SOC_VPIF_0_REGS,VPIF_REQSIZE_TWO_FIFTY_SIX);
VPIFEmulationControlSet(SOC_VPIF_0_REGS, VPIF_HALT);
// Initialize buffer addresses for the frame
VPIFCaptureFBConfig(SOC_VPIF_0_REGS,VPIF_CHANNEL_0, VPIF_TOP_FIELD, VPIF_LUMA, (unsigned int)picBuf1, 2*VBUF_SIZE);
VPIFCaptureFBConfig(SOC_VPIF_0_REGS,VPIF_CHANNEL_1, VPIF_TOP_FIELD, VPIF_LUMA, (unsigned int)picBuf1, 2*VBUF_SIZE);
// Type of the memory organization
VPIFCaptureFieldframeModeSelect(SOC_VPIF_0_REGS,VPIF_FRAME_BASED);
// No YC muxed mode
VPIFCaptureYcmuxModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_YC_NONMUXED);
VPIFCaptureYcmuxModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_1, VPIF_YC_NONMUXED);
// Enable interrupt FRAME0
VPIFInterruptEnable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 | VPIF_FRAMEINT_CH1 );
VPIFInterruptEnableClear(SOC_VPIF_0_REGS,VPIF_FRAMEINT_CH0|VPIF_FRAMEINT_CH1|VPIF_FRAMEINT_CH2|VPIF_FRAMEINT_CH3|VPIF_ERROR_INT); //Clear all interrupts
VPIFInterruptEnableSet(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0 | VPIF_FRAMEINT_CH1);
// Enable capture
VPIFCaptureChanenEnable(SOC_VPIF_0_REGS, VPIF_CHANNEL_0);
VPIFCaptureChanenEnable(SOC_VPIF_0_REGS, VPIF_CHANNEL_1);
}
/*
* Initialize capture
*/
void SetUpVPIFRx(void)
{
// Disable interrupts
VPIFInterruptDisable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH1);
VPIFInterruptDisable(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0);
// Disable capture ports
VPIFCaptureChanenDisable(SOC_VPIF_0_REGS, VPIF_CHANNEL_1);
VPIFCaptureChanenDisable(SOC_VPIF_0_REGS, VPIF_CHANNEL_0);
// config dma request size and emulation control.
VPIFDMARequestSizeConfig(SOC_VPIF_0_REGS, VPIF_REQSIZE_TWO_FIFTY_SIX);
VPIFEmulationControlSet(SOC_VPIF_0_REGS, VPIF_FREE);
// Set Clock to FALLING EDGE (calling RISING because TI messed things up and mixed the parameters)
//VPIFCaptureClkedgeModeSelect(SOC_VPIF_0_REGS,VPIF_CHANNEL_0,VPIF_CLKEDGE_RISING);
//VPIFCaptureClkedgeModeSelect(SOC_VPIF_0_REGS,VPIF_CHANNEL_1,VPIF_CLKEDGE_RISING);
//HVALID and VVALID inversion
VPIFCaptureRawVvinvSet(SOC_VPIF_0_REGS,VPIF_RAW_VVALID_INVERT);
// Interrupt every 720 lines
VPIFCaptureRawIntlineConfig(SOC_VPIF_0_REGS,720);
/*///////////Horizontal ancillary enable
VPIFCaptureHancEnable(SOC_VPIF_0_REGS,VPIF_CHANNEL_0);
VPIFCaptureHancEnable(SOC_VPIF_0_REGS,VPIF_CHANNEL_1);
////////Vertical ancillary enable
VPIFCaptureVancEnable(SOC_VPIF_0_REGS,VPIF_CHANNEL_0);
VPIFCaptureVancEnable(SOC_VPIF_0_REGS,VPIF_CHANNEL_1);*/
////// Y/C MUX mode
VPIFCaptureYcmuxModeSelect(SOC_VPIF_0_REGS,VPIF_CHANNEL_0,VPIF_YC_NONMUXED);
VPIFCaptureYcmuxModeSelect(SOC_VPIF_0_REGS,VPIF_CHANNEL_1,VPIF_YC_NONMUXED);
// Interrupt after capturing the bottom field of every frame
VPIFCaptureIntframeConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_FRAME_INTERRUPT_TOP);
VPIFCaptureIntframeConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_1, VPIF_FRAME_INTERRUPT_TOP);
// RAW mode
VPIFCaptureCapmodeModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_CAPTURE_RAW);
VPIFCaptureCapmodeModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_1, VPIF_CAPTURE_RAW);
VPIFCaptureModeConfig(SOC_VPIF_0_REGS, VPIF_CAPTURE_RAW, VPIF_CHANNEL_0, 0, (VPIFVbufParam*) 0);
VPIFCaptureModeConfig(SOC_VPIF_0_REGS, VPIF_CAPTURE_RAW, VPIF_CHANNEL_1, 0, (VPIFVbufParam*) 0);
// 8 bits bit data
VPIFCaptureRawDatawidthConfig(SOC_VPIF_0_REGS,VPIF_RAW_EIGHT_BPS);
// Progressive capture
VPIFCaptureIntrprogModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_CAPTURE_PROGRESSIVE);
VPIFCaptureIntrprogModeSelect(SOC_VPIF_0_REGS, VPIF_CHANNEL_1, VPIF_CAPTURE_PROGRESSIVE);
// Change to Frame based for Progressive Scan
VPIFCaptureFieldframeModeSelect(SOC_VPIF_0_REGS,VPIF_FRAME_BASED);
printf("VPIF RX\r\n");
}
void configReceivePinMux(void)
{
EVMOMAPL138_pinmuxConfig(PINMUX_VPIF_RX_REG_0, PINMUX_VPIF_RX_MASK_0, PINMUX_VPIF_RX_VAL_0);
EVMOMAPL138_pinmuxConfig(PINMUX_VPIF_RX_REG_1, PINMUX_VPIF_RX_MASK_1, PINMUX_VPIF_RX_VAL_1);
EVMOMAPL138_pinmuxConfig(PINMUX_VPIF_RX_REG_2, PINMUX_VPIF_RX_MASK_2, PINMUX_VPIF_RX_VAL_2);
}
