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C6678 SRIO endianess

YUCHAO WANG
Expert 1265 points

Hi TI engineer,

          As described in SRIO User Guide Chapter 2.8, when C6678 works in little endian, endian-conversion will be handled by the peripheral.But I cannot understand the process clearly.

         The figure shows how 128 bit in VBUS changed to the data stream in SRIO packet.I want to know if B0 - B15 is the memory address?For example,if there is the data in the memory:

         Addr1   Addr1+1  ......   Addr1+15

          0x0         0x1        ......         0xf

         And we assume the swap mode is mode A. Then what will the data stream be in the packet?Who is the first Data in the port?

         Thank you very much,looking forward to the reply.

         Regards.

  • 0
    TI__Mastermind 23525 points

    Assume you mean ch 2.3.8.  In Figure 2-26, it is showing how the internal bus byte lanes are mapped to the out-going RapidIO packet for both little endian and big endian systems.  B0-B15 are byte lanes not memory addresses, and yes they represent data in those lanes.  We don't do any bit swizzling within a byte.  Mode A is the most common used and the figure shows the order of the bytes within the packet based on the mode.  Essentially, mode A will place the same data byte in the same byte memory address when translating endianness.

    Regards,

    Travis

  • 0 in reply to tscheck
    Expert 1265 points

    Hi Travis

            Thank you for answering.Since B0 - B15 is the data in lanes, I am puzzled by such questions:

            1. Does bit map in VBUS map to the memory address? In other words, does VBUS 7:0 stored in Addr, VBUS15:8 stored in Addr+1?

            2. Does the endianess reverse executed automatically when C6678 in little endianess? When C6678 in mode A, can we make sure that any transfer between any C6678, no matter they have same endianess or different endianess, the transfer will be byte-to-byte orderly?

            3.Is the same kind of reverse handled in any device in little endianess who has srio peripheral ?

            Regards,

            Yuchao

  • 0 in reply to YUCHAO WANG
    TI__Mastermind 23525 points

    Yuchao,

    Honestly, the easiest way to understand the endianness conversion when in little endian, is to run a few quick examples on the EVM.  I'd suggest you start with the MCSDK DIOloopback example.

    YUCHAO WANG said:
    1. Does bit map in VBUS map to the memory address? In other words, does VBUS 7:0 stored in Addr, VBUS15:8 stored in Addr+1?

    Yes, in little endian.  Look at figure 2-26.

    YUCHAO WANG said:
    2. Does the endianess reverse executed automatically when C6678 in little endianess? When C6678 in mode A, can we make sure that any transfer between any C6678, no matter they have same endianess or different endianess, the transfer will be byte-to-byte orderly?

    Yes, it is done automatically.  If in big endian, there is no translation. Yes, in mode at the bytes order and address are maintained.

    YUCHAO WANG said:
    3.Is the same kind of reverse handled in any device in little endianess who has srio peripheral ?

    I'm not certain how other devices handle it.  But, SRIO packets are always big endian format, so any little endian device must translate.  The question will be what boundary (element size) are they translating on.  If it is byte element size, it should all work.

    Regards,

    Travis

  • 0 in reply to tscheck
    Expert 1265 points

    Thank you very much for your reply.I think I have comprehended the whole principle of the endianess.