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AM1808 Asynchronous Memory Operation with Extended Wait Mode

Daisuke Maeda
Guru 20205 points

The minimum timing requirement for EM_WAIT pulse duration is 2 EMA_CLK period.
When EM_WAIT is less than 2 EMA_CLK period, may the Extended Wait be performed?

Our customer traced the Asynchronous Memory Write Timing with Extended Wait Mode. It as follows:

 EMA_CLK clock frequency: 62.5MHz (16nsec)

 CE3CFG.W_SETUP：1 EMA_CLK period
 CE3CFG.W_STROBE：4 EMA_CLK period
 CE3CFG.W_HOLD：1 EMA_CLK period

 AWCC.CS3_WAIT:01b (EMA_WAIT[1] pin is used)
 AWCC.WP1: 0b (EMA_WAIT[1] pin is low)
 AWCC.MAX_EXT_WAIT: 80h

The strobe period is expanded to 5 EMA_CLK period. While EMA_CS3 is asserted, the duration of asserted EM_WAIT is less than 2 EMA_CLK period.

Best regards,

Daisuke

 

  • 0
    TI__Expert 4760 points

    Hi Daisuke,

    Out of three signals you have mentioned (CS3_N, WE_N, and WAIT), which signal the customer used as a triggering source to capture this waveform.

    It looks like the WAIT signal asserted before the CS3_N asserts.

    The external device assert EMA_WAIT signal that should not be asserted before the CS3 signal

    Which device they are hooked up on this peripheral?

    Regards

    Antony

  • 0 in reply to Antony Samsunil
    Guru 20205 points

    Hi Antony,

    Thank you for your reply.

    EMIFA is connected to FPGA with the Asynchronous memory interface.

    I suggested to our customer modifying FPGA.

    Best regards,

    Daisuke