C6636 PLL configuration

Heekook,

The regisgters you mentioned above are for TI's KeyStone I device (such as 6678), but TI's KeyStone II devices, (TCI6636K2H is one of KeyStone II devices) use different SerDes, and require different way to configure them.

In general, configuring SerDes on KeyStone II devices requires:

1. Load a default SerDes PHY configurations specific to each interface through
   TI-provided APIs supplied as part of MCSDK (this step involves some writes to
   reserved bit-fields as well).
2. Optimize TX and RX channel equalization parameters (such as the TX FIR Filter
   Coefficients or the RX ATT and BOOST) to a specific hardware platform.

Since the default SerDes configurations provided for KeyStone II family are expected to work on user platforms with little or no optimization. TI requires customers to use TI-generated and supported default PHY configurations(supplied as part of MCSDK).

Back to your specific quesiton, the solution is in the MCSDK release - using the API to program the SerDes. Following is an example:

               csl_retval = CSL_EthernetSerdesInit(
                                                   CSL_NETCP_SERDES_CFG_REGS, 
                                                   CSL_SERDES_REF_CLOCK_125M, // or CSL_SERDES_REF_CLOCK_156p25M,
                                                   CSL_SERDES_LINK_RATE_1p25G
                                            );

For more details, you can take a look at the file - \packages\ti\csl\src\ip\serdes_sb\V0\csl_serdes_ethernet.h in the MCSDK release you have.

Regards!
Wen