Setting the McASP TimeSlot register RTDM

Martin H.

Other Parts Discussed in Thread: PCM4204

Hi,

having posted the following question in the StarterWare Forum there was no feedback. So perhaps this forum is the better place for it.

I am trying to modify the Starterware McASP example I am not sure how to set the receive TDM time slot register (RTDM) correctly:
The aim is just to receive 4 adc channels from 2 I2S lines (no TX activity as demonstrated in the example).
The number of I2S data lines has been increased from 1 to 2. AXR(0) and AXR(1) shall be the receive serializers.
Per I2S signal there is a left and right signal with 24 bits each.

Would it be correct to set the slot register RTDM to 0x0F?
I.e. 4 slots 3...0 with 4 adc channels?

SDOUT1 and SDOUT2 are the data lines representing the I2S signals (coming out from an adc PCM4204).
How can I make sure that the data always is received in the same order? All 4 channels are sampled
simoultaneously.

Any help would be appreciated.

Thank you.

Regards,
Martin H.

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Hi Martin,

The Starterware forum is the correct place for Starterware related questions. This forum supports only the TI distributed Linux EZSDK.

0 Martin H. over 11 years ago in reply to Biser Gatchev-XID

Expert 2315 points

Hi Biser,

I considered it as a more processor related question (How does the processor behave if ...? What values are
expected in the RTDM register?). That is why I placed it in the Sitara Processors Forum.
Can we agree not to delete that threat in this forum immediately?
It might increase the chance to get a response at all.

Thanks.

Regards,
Martin

0 Biser Gatchev-XID over 11 years ago in reply to Martin H.

TI__Guru**** 393215 points

We will definitely not delete it. Usual procedure is to move the thread to the relevant forum, but you said you have already posted on the Starterware forum so we'll keep this thread here. I will try to search for information that can help you.

0 Biser Gatchev-XID over 11 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Hi Martin,

As I see it from reading the AM335X TRM Rev. J, each bit of the RTDM register corresponds to the TDM slot with the same number (e.g. RTDM bit 26 corresponds to receive TDM slot 26). If the bit is programmed to 1 then the corresponding receive TDM slot is active and the receive serializer shifts in data during this slot.

From your example value 0x0F, this would mean that data is shifted in during slots 0, 1, 2 and 3.

0 Martin H. over 11 years ago in reply to Biser Gatchev-XID

Expert 2315 points

Hi Biser,

what a fast reply!!!
So that is clear and brings me to the second part of the question.

Now there is 1 I2S signal named SDOUT1 connected to AXR0 and another one SDOUT2 connected to AXR1. Each I2S signal has 2 time slots (2 adc channels) - 4 all together. SDOUT1 and SDOUT2 are generated simultaneously.
Which adc channel is assigned to which time slot? SDOUT1 to time slot 0 and 1?
In what order is data written to the FIFO? Can I influence that order or must I fear that sometimes SDOUT1 comes first and the next time it is SDOUT2?
That is something that still confuses me.

Thanks for your trouble!

Regards,
Martin H.

0 Biser Gatchev-XID over 11 years ago in reply to Martin H.

TI__Guru**** 393215 points

I can't help on this one. Please refer to the AM335X Technical Reference Manual Rev. J (http://www.ti.com/lit/ug/spruh73j/spruh73j.pdf). Section 22 covers the McASP. See subsection 22.3.3.1.2 for I2S details.

0 Biser Gatchev-XID over 11 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

By the way, I think that for I2S you will need to set RTDM to 0x03, not 0x0F.

0 Martin H. over 11 years ago in reply to Biser Gatchev-XID

Expert 2315 points

Even if I have 2 I2S lines? Each signal has 2 time slots!?

Regards,

Martin H.

0 Biser Gatchev-XID over 11 years ago in reply to Martin H.

TI__Guru**** 393215 points

From AM335X TRM:

22.3.3.1.2 Inter-Integrated Sound (I2S) Format

The inter-integrated sound (I2S) format is used extensively in audio interfaces. The TDM transfer mode of the McASP supports the I2S format when configured to 2 slots per frame.

The AXR inputs are working in parallel, using the same bit clock and frame sync.

0 Martin H. over 11 years ago in reply to Biser Gatchev-XID

Expert 2315 points

I see.
So each serializer creates its own interrupt/event to initialize data transfer and every serializer's data has to be handled separately, I assume.
But as RTDM only exists once, that would mean that the time slots activated are valid for all active serializers AXRn. With
other words it is not possible to activate only time slot 0 for AXR0 and only time slot 1 for AXR1.

Is that correct?

Regards,

Martin

0 Biser Gatchev-XID over 11 years ago in reply to Martin H.

TI__Guru**** 393215 points

Yes, this is correct. The receive serializers within a single McASP module are using the same clock and sync.

0 Martin H. over 11 years ago in reply to Biser Gatchev-XID

Expert 2315 points

Hi Biser,

the definition

      #define I2S_SLOTS ((1 << NUM_I2S_CHANNELS) - 1)

from the StarterWare McASP example is a bit missleading.

It seems that NUM_I2S_CHANNELS is always meant to be 2 independent of the number of serializers.

I2S_SLOTS is the mask for the RTDM register and assuming that NUM_I2S_CHANNELS is 4 (i.e. two I2S signals), the result would be 0x0f instead of 3.
(For the StarterWare example, where NUM_I2S_CHANNELS=2, the result is 3, so it is ok.)

Thank you very much for your help!

Regards,
Martin

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Setting the McASP TimeSlot register RTDM